公开(公告)号：US20060112133A1

公开(公告)日：2006-05-25

申请号：US11259986

申请日：2005-10-26

Applicant: Philip Ljubicich ,  David Camarillo ,  Pankaj Kumar

Inventor： Philip Ljubicich ,  David Camarillo ,  Pankaj Kumar

IPC: G06F17/00 ,  G06F7/00

CPC classification number: G06F16/9024

Abstract: In one example, a system receives, from different sources, data having various formats, the received data is selected and combined in accordance with the invention to create accurate records. Specifically, the inventive system organizes the received data into uniform data records having a predetermined format. The data in the uniform data records is converted, if necessary, to conform to a predetermined nomenclature, resulting in normalized data records. The normalized data records are then processed to extract and/or deduce information desired by users.

Abstract translation: 在一个示例中，系统从不同的源接收具有各种格式的数据，根据本发明选择和组合接收的数据以创建准确的记录。 具体地，本发明的系统将接收到的数据组织成具有预定格式的统一数据记录。 如果需要，统一数据记录中的数据被转换成符合预定的命名，导致归一化的数据记录。 然后处理归一化的数据记录以提取和/或推导出用户期望的信息。

公开(公告)号：US20140189212A1

公开(公告)日：2014-07-03

申请号：US13976262

申请日：2011-09-30

Applicant: Thomas M. Slaight ,  Sivakumar Radhakrishnan ,  Mark Schmisseur ,  Pankaj Kumar ,  Saptarshi Mondal ,  Sin S. Tan ,  David C. Lee ,  Marc T. Jones ,  Geetani R. Edirisooriya ,  Bradley A. Burres ,  Brian M. Leitner ,  Kenneth C. Haren ,  Michael T. Klinglesmith ,  Matthew R. Wilcox ,  Eric J. Dahlen

Inventor： Thomas M. Slaight ,  Sivakumar Radhakrishnan ,  Mark Schmisseur ,  Pankaj Kumar ,  Saptarshi Mondal ,  Sin S. Tan ,  David C. Lee ,  Marc T. Jones ,  Geetani R. Edirisooriya ,  Bradley A. Burres ,  Brian M. Leitner ,  Kenneth C. Haren ,  Michael T. Klinglesmith ,  Matthew R. Wilcox ,  Eric J. Dahlen

IPC: G06F3/06 ,  G06F11/10 ,  G06F13/28

CPC classification number: G06F13/28 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0626 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/1068 ,  G06F12/0866 ,  G06F13/102 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/262 ,  G06F2213/0026 ,  G06F2213/0032

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Abstract translation: 根据本文公开的实施例，提供了用于在逻辑驱动器模型下呈现直接访问存储的方法，系统，机制，技术和装置; 实现用于协作NVM数据保护的分布式架构; 数据镜像，以保持一致的SSD延迟; 通过并发RAID处理来提升控制器的性能和支持DIF的RAS; 执行门铃机制的仲裁和资源计划，包括门铃仲裁以公平和防止冲突拥堵; 并且通过使用中断合并方案在控制器中实现使用消息传送单元和NTB的多个中断生成。

公开(公告)号：US08701189B2

公开(公告)日：2014-04-15

申请号：US12322321

申请日：2009-01-29

Applicant: Suman Saraf ,  Sharad Agrawal ,  Pankaj Kumar

Inventor： Suman Saraf ,  Sharad Agrawal ,  Pankaj Kumar

IPC: G06F21/00

CPC classification number: G06F21/566

Abstract: A method of and system for protecting a computer system against denial-of-service attacks or other exploitation. The method comprises collecting network data and analyzing the network data using statistical and heuristic techniques to identify the source of the exploitation upon receiving an indication of exploitation. Upon identifying the network source, the network data associated with the network is blocked, redirected, or flow controlled. Preferably, the method also includes identifying when the system is being exploited.

Abstract translation: 一种用于保护计算机系统免遭拒绝服务攻击或其他开发的方法和系统。 该方法包括收集网络数据并使用统计和启发式技术分析网络数据，以便在接收到开发指示时识别开发的来源。 在识别网络源时，与网络相关联的网络数据被阻塞，重定向或流量控制。 优选地，该方法还包括识别系统什么时候被利用。

公开(公告)号：US08607129B2

公开(公告)日：2013-12-10

申请号：US13175500

申请日：2011-07-01

Applicant: Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

Inventor： Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

IPC: H03M13/00 ,  G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1076 ,  H03M1/1052 ,  H03M7/42 ,  H03M13/09 ,  H03M13/091 ,  H03M13/158 ,  H03M13/6575

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

公开(公告)号：US08583984B2

公开(公告)日：2013-11-12

申请号：US12976247

申请日：2010-12-22

Applicant: Mark A. Schmisseur ,  Sivakumar Radhakrishnan ,  Pankaj Kumar ,  Marc A. Goldschmidt ,  Peter Molnar

Inventor： Mark A. Schmisseur ,  Sivakumar Radhakrishnan ,  Pankaj Kumar ,  Marc A. Goldschmidt ,  Peter Molnar

IPC: H03M13/00

CPC classification number: G06F11/1076

Abstract: A method and apparatus to enable data integrity checking of a block of data while the block of data is being transferred from a volatile memory to a non-volatile storage device is provided. The data integrity checking is performed in conjunction with Direct Memory Access operations and Redundant Array of Independent Disk (RAID) operations. In addition, data integrity checking of syndrome blocks in the RAID is performed during transfers to/from the storage devices in the RAID system and during RAID update and RAID data reconstruction operations.

Abstract translation: 提供了一种方法和装置，用于在数据块从易失性存储器传输到非易失性存储装置的同时使数据块的数据完整性检查得以实现。 数据完整性检查与直接内存访问操作和独立磁盘冗余阵列（RAID）操作一起执行。 此外，在向RAID系统的存储设备传输期间以及在RAID更新和RAID数据重建操作期间执行RAID中的校验块的数据完整性检查。

公开(公告)号：US20130247181A1

公开(公告)日：2013-09-19

申请号：US12322321

申请日：2009-01-29

Applicant: Suman Saraf ,  Sharad Agrawal ,  Pankaj Kumar

Inventor： Suman Saraf ,  Sharad Agrawal ,  Pankaj Kumar

IPC: G06F21/00

CPC classification number: G06F21/566

Abstract: A method of and system for protecting a computer system against denial-of-service attacks or other exploitation. The method comprises collecting network data and analyzing the network data using statistical and heuristic techniques to identify the source of the exploitation upon receiving an indication of exploitation. Upon identifying the network source, the network data associated with the network is blocked, redirected, or flow controlled. Preferably, the method also includes identifying when the system is being exploited.

Abstract translation: 一种用于保护计算机系统免遭拒绝服务攻击或其他开发的方法和系统。 该方法包括收集网络数据并使用统计和启发式技术分析网络数据，以便在接收到开发指示时识别开发的来源。 在识别网络源时，与网络相关联的网络数据被阻塞，重定向或流量控制。 优选地，该方法还包括识别系统什么时候被利用。

公开(公告)号：US20130185570A1

公开(公告)日：2013-07-18

申请号：US13785108

申请日：2013-03-05

Applicant: Pankaj Kumar ,  Hang T. Nguyen ,  Christopher Houghton ,  David A. Biermann

Inventor： Pankaj Kumar ,  Hang T. Nguyen ,  Christopher Houghton ,  David A. Biermann

IPC: G06F1/26

CPC classification number: G06F1/3296 ,  G05F1/46 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F9/3016 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.

公开(公告)号：US08441281B2

公开(公告)日：2013-05-14

申请号：US13165500

申请日：2011-06-21

Applicant: Makeshwar Kothandaraman ,  Pankaj Kumar ,  Paul K. Hartley ,  John Christopher Kriz

Inventor： Makeshwar Kothandaraman ,  Pankaj Kumar ,  Paul K. Hartley ,  John Christopher Kriz

IPC: H03K19/003 ,  H03K19/094 ,  H03K19/0175

CPC classification number: H03K19/09432 ,  H03K19/018528

Abstract: A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively. The first switching element is operative to electrically connect the first differential output to the second voltage source when the first transistor is turned off. The second switching element is operative to electrically connect the second differential output to the second voltage source when the second transistor is turned off.

Abstract translation: 具有增加的输出电压摆幅的差分缓冲电路包括至少包括第一和第二晶体管的差分输入级，第一和第二晶体管分别用于接收第一和第二信号。 缓冲电路还包括连接在差分输入级与第一电压源之间的偏置级。 偏置级用于产生作为提供给偏置级的第三信号的函数的静态电流。 负载电路连接在第二电压源和差分输入级之间，缓冲电路的第一和第二差分输出在负载电路和差分输入级之间的结点处产生。 负载电路分别包括与第一和第二晶体管耦合的第一和第二开关元件。 当第一晶体管截止时，第一开关元件可操作以将第一差分输出电连接到第二电压源。 当第二晶体管截止时，第二开关元件可操作以将第二差分输出电连接到第二电压源。

公开(公告)号：US20130021085A1

公开(公告)日：2013-01-24

申请号：US13186310

申请日：2011-07-19

Applicant: Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

Inventor： Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

IPC: H03L5/00

CPC classification number: H03K3/356113

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.

Abstract translation: 用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，输入级至少包括第一和第二节点， 第二节点是第一节点处的电压的逻辑补码。 负载电路与输入级耦合，负载电路可操作以至少临时存储指示输入信号的逻辑状态的第一和/或第二节点处的信号。 与第二节点连接的输出级可操作以产生指示输入信号的逻辑状态的输出信号。 电压电平转换器电路还包括与输出级连接的补偿电路，并且可操作以平衡电压电平转换器电路中的上拉和下拉传播延迟作为第一节点处的电压的函数。

公开(公告)号：US20130007573A1

公开(公告)日：2013-01-03

申请号：US13175500

申请日：2011-07-01

Applicant: Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

Inventor： Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

IPC: H03M13/09 ,  G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1076 ,  H03M1/1052 ,  H03M7/42 ,  H03M13/09 ,  H03M13/091 ,  H03M13/158 ,  H03M13/6575

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

Abstract translation: 本公开的实施例描述了使用伽罗瓦域算术的循环冗余校验电路的方法，装置和系统配置。