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公开(公告)号：US20130234340A1
公开(公告)日：2013-09-12
申请号：US13857077
申请日：2013-04-04
Applicant: QUALCOMM INCORPORATED
Inventor： Jungwon Suh
IPC: H01L25/065 , G06F17/50
CPC classification number: H01L25/0657 , G06F17/5077 , G11C5/02 , G11C8/12 , G11C16/20 , H01L23/481 , H01L25/18 , H01L2224/16145 , H01L2225/06527 , H01L2225/06541 , H01L2924/15311
Abstract: A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact.
Abstract translation: 公开了具有芯片标识符结构的可垂直堆叠的管芯。 在一个具体实施例中，公开了一种半导体器件，其包括具有第一至第二硅通孔的管芯以传送芯片标识符和其它数据。 半导体器件还包括芯片标识符结构，其包括至少两个穿过硅通孔，每个硅通孔硬接线到外部电触头。
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公开(公告)号：US20250111885A1
公开(公告)日：2025-04-03
申请号：US18978617
申请日：2024-12-12
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , Dexter Tamio Chun , Anand Srinivasan , Olivier Alavoine , Laurent Rene Moll
Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.
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公开(公告)号：US20250068574A1
公开(公告)日：2025-02-27
申请号：US18454658
申请日：2023-08-23
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , Pankaj Deshmukh , Subbarao Palacharla , Alain Artieri
IPC: G06F13/16 , G06F1/3234 , G06F13/28
Abstract: This disclosure provides systems, methods, and devices for memory systems that support an efficient mode for reducing power consumption in a memory module while maintaining access to all contents of memory. In a first aspect, a method includes communicating, by a memory module, first data stored in a first plurality of banks to a host device through a first sub-channel in a first operating mode; communicating second data stored in the second plurality of banks to the host device through a second sub-channel in the first operating mode; receiving a command to enter a second operating mode; and communicating third data stored in the first plurality of banks and fourth data stored in the second plurality of banks to the host device through the first sub-channel in the second operating mode. Other aspects and features are also claimed and described.
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公开(公告)号：US12230347B2
公开(公告)日：2025-02-18
申请号：US18322997
申请日：2023-05-24
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , Dexter Tamio Chun , Anand Srinivasan , Olivier Alavoine , Laurent Rene Moll
Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.
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公开(公告)号：US12159033B2
公开(公告)日：2024-12-03
申请号：US18047493
申请日：2022-10-18
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , Pankaj Deshmukh , Michael Hawjing Lo , Subbarao Palacharla , Olivier Alavoine
IPC: G06F3/06
Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method of handling data and metadata at a memory device includes receiving data from the host via the at least one data connection into the first plurality of registers; receiving metadata from the host via the at least one non-data connection into the second plurality of registers; storing the data in the first portion of the memory array; and storing the metadata in the second portion of the memory array. Other aspects and features are also claimed and described.
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Patent Agency Ranking
公开(公告)号：US20240385747A1
公开(公告)日：2024-11-21
申请号：US18320492
申请日：2023-05-19
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , Michael Hawjing Lo
IPC: G06F3/06
Abstract: This disclosure provides systems, methods, and devices for memory systems that support metadata. In a first aspect, a method includes receiving, from a host, a message comprising instructions to configure a first portion of a memory array for storage of data and metadata and to configure a second portion of the memory array for storage of only data and configuring the memory array in accordance with the received message. Other aspects and features are also claimed and described.
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公开(公告)号：US20240304271A1
公开(公告)日：2024-09-12
申请号：US18668593
申请日：2024-05-20
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh
CPC classification number: G11C29/42 , G11C7/1048 , G11C7/1063 , G11C8/18 , G11C29/1201
Abstract: A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.
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公开(公告)号：US20230305971A1
公开(公告)日：2023-09-28
申请号：US17650455
申请日：2022-02-09
Applicant: QUALCOMM Incorporated
Inventor： Pankaj Deshmukh , Shyamkumar Thoziyoor , Vishakh Balakuntalam Visweswara , Jungwon Suh , Subbarao Palacharla
IPC: G06F13/16
CPC classification number: G06F13/1668
Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.
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59.发明公开公开(公告)号：US20230298682A1
公开(公告)日：2023-09-21
申请号：US18322997
申请日：2023-05-24
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , Dexter Tamio Chun , Anand Srinivasan , Olivier Alavoine , Laurent Rene Moll
CPC classification number: G11C29/42 , G11C29/44 , G11C7/1045 , G11C29/18 , G11C2029/1202
Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.
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公开(公告)号：US20230170037A1
公开(公告)日：2023-06-01
申请号：US17658846
申请日：2022-04-12
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh
CPC classification number: G11C29/42 , G11C7/1048 , G11C7/1063 , G11C8/18 , G11C29/1201
Abstract: A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.
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