公开(公告)号：US07015078B1

公开(公告)日：2006-03-21

申请号：US10658668

申请日：2003-09-09

申请人： Qi Xiang ,  Jung-Suk Goo ,  James Pan

发明人： Qi Xiang ,  Jung-Suk Goo ,  James Pan

IPC分类号： H01L21/00

CPC分类号： H01L29/78603 ,  H01L21/76254 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78687

摘要： A silicon on insulator (SOI) substrate includes a layer of silicon carbide beneath an insulating layer on which semiconductor devices are formed. The silicon carbide layer has a high thermal conductivity and provides beneficial dissipation of thermal energy generated by the devices. The SOI substrate may be formed by a bonding method. SOI MOSFET devices using the SOI substrate are also disclosed.

摘要翻译： 绝缘体上硅（SOI）衬底包括在其上形成有半导体器件的绝缘层下方的碳化硅层。 碳化硅层具有高导热性，并提供由器件产生的热能的有益耗散。 SOI衬底可以通过接合方法形成。 还公开了使用SOI衬底的SOI MOSFET器件。

公开(公告)号：US06984569B2

公开(公告)日：2006-01-10

申请号：US10642916

申请日：2003-08-18

申请人： Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

发明人： Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

IPC分类号： H01L21/8224

CPC分类号： H01L29/7842 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

公开(公告)号：US06962857B1

公开(公告)日：2005-11-08

申请号：US10358966

申请日：2003-02-05

申请人： Minh-Van Ngo ,  Ming-Ren Lin ,  Eric N. Paton ,  Haihong Wang ,  Qi Xiang ,  Jung-Suk Goo

发明人： Minh-Van Ngo ,  Ming-Ren Lin ,  Eric N. Paton ,  Haihong Wang ,  Qi Xiang ,  Jung-Suk Goo

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in a strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be an LPCVD. An annealing step can be utilized to form the liner.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由沉积在低温过程中的层形成，其减少锗除气。 低温过程可以是LPCVD。 可以使用退火步骤来形成衬垫。

公开(公告)号：US06924182B1

公开(公告)日：2005-08-02

申请号：US10642375

申请日：2003-08-15

申请人： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Eric N. Paton ,  Haihong Wang

发明人： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Eric N. Paton ,  Haihong Wang

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/76

CPC分类号： H01L21/823878 ,  H01L21/76237 ,  H01L21/823807

摘要： The formation of shallow trench isolations in a strained silicon MOSFET includes performing ion implantation in the strained silicon layer in the regions to be etched to form the trenches of the shallow trench isolations. The dosage of the implanted ions and the energy of implantation are chosen so as to damage the crystal lattice of the strained silicon throughout the thickness of the strained silicon layer in the shallow trench isolation regions to such a degree that the etch rate of the strained silicon in those regions is increased to approximately the same as or greater than the etch rate of the underlying undamaged silicon germanium. Subsequent etching yields trenches with significantly reduced or eliminated undercutting of the silicon germanium relative to the strained silicon. This in turn substantially prevents the formation of fully depleted silicon on insulator regions under the ends of the gate, thus improving the MOSFET leakage current.

摘要翻译： 应变硅MOSFET中的浅沟槽隔离的形成包括在被蚀刻的区域中的应变硅层中执行离子注入以形成浅沟槽隔离的沟槽。 选择注入离子的剂量和注入能量，以便在浅沟槽隔离区域中的应变硅层的整个厚度上损坏应变硅的晶格，使得应变硅的蚀刻速率 在这些区域中增加到大致等于或大于底层未损坏的硅锗的蚀刻速率。 随后的蚀刻产生相对于应变硅显着减少或消除硅锗底切的沟槽。 这又大大防止了在栅极端部的绝缘体区域上形成完全耗尽的硅，从而改善MOSFET漏电流。

公开(公告)号：US06905923B1

公开(公告)日：2005-06-14

申请号：US10619877

申请日：2003-07-15

申请人： Eric N. Paton ,  Haihong Wang ,  Qi Xiang

发明人： Eric N. Paton ,  Haihong Wang ,  Qi Xiang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823864

摘要： A method of fabricating an SMOS integrated circuit with source and drain junctions utilizes an offset gate spacer for N-type transistors. Ions are implanted to form the source and drain regions in a strained layer. The offset spacer reduces problems associated with Arsenic (As) diffusion on strained semiconductor layers. The process can be utilized for SMOS metal oxide semiconductor field effect transistors (MOSFETs). The strained layer can be a strained silicon layer formed above a germanium layer.

摘要翻译： 制造具有源极和漏极结的SMOS集成电路的方法利用用于N型晶体管的偏移栅极间隔物。 植入离子以形成应变层中的源区和漏区。 偏移间隔物减少了在应变半导体层上与砷（As）扩散相关的问题。 该工艺可用于SMOS金属氧化物半导体场效应晶体管（MOSFET）。 应变层可以是形成在锗层之上的应变硅层。

公开(公告)号：US20050124097A1

公开(公告)日：2005-06-09

申请号：US10729194

申请日：2003-12-05

申请人： Qi Xiang

发明人： Qi Xiang

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L21/479 ,  H01L21/326 ,  H01L21/82 ,  H01L29/00

CPC分类号： H01L21/76888 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of programming a fuse utilizes a fuse including a material having a first phase and a second phase. The first phase has a different resistivity than the second phase. The method includes providing a current or voltage to the fuse and changing the material from the first phase to the second phase with the current. The material can be a silicide material such as nickel silicide.

摘要翻译： 熔丝编程方法利用包括具有第一相和第二相的材料的熔丝。 第一相具有与第二相不同的电阻率。 该方法包括向保险丝提供电流或电压，并用电流将材料从第一相改变到第二相。 该材料可以是硅化物材料，例如硅化镍。

公开(公告)号：US06897122B1

公开(公告)日：2005-05-24

申请号：US10747205

申请日：2003-12-30

申请人： Qi Xiang

发明人： Qi Xiang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： The present invention enables the production of improved high-speed semiconductor devices. The present invention provides the higher speed offered by strained silicon technology coupled with the smaller overall device size provided by shallow trench isolation technology without relaxation of the portion of the strained silicon layer adjacent to a shallow trench isolation region by laterally extending a shallow trench isolation into the strained silicon layer overlying a silicon germanium layer.

摘要翻译： 本发明能够制造改进的高速半导体器件。 本发明提供了由应变硅技术提供的更高速度，以及由浅沟槽隔离技术提供的较小的整体器件尺寸，而不会通过将浅沟槽隔离横向延伸到浅沟槽隔离部分而使弛豫与浅沟槽隔离区域相邻的应变硅层的部分松弛 覆盖硅锗层的应变硅层。

公开(公告)号：US06893929B1

公开(公告)日：2005-05-17

申请号：US10641548

申请日：2003-08-15

申请人： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Haihong Wang

发明人： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Haihong Wang

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/10

CPC分类号： H01L29/6659 ,  H01L21/76237 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7842 ,  Y10S438/933

摘要： The formation of shallow trench isolations in a strained silicon MOSFET includes implantation of a dopant into overhang portions of the strained silicon layer and silicon germanium layer at the edges of trenches in which shallow trench isolations are to be formed. The conductivity type of the dopant is chosen to be opposite the conductivity type of the source and drain dopants. The implanted dopant increases the threshold voltage Vt beneath the ends of the gate in overhang portions of the strained silicon layer so that it is approximately equal to or greater than that of the remainder of the MOSFET. The resulting strained silicon MOSFET exhibits reduced leakage current beneath the ends of the gate.

摘要翻译： 应变硅MOSFET中浅沟槽隔离的形成包括将掺杂剂注入到将要形成浅沟槽隔离的沟槽边缘处的应变硅层和硅锗层的伸出部分。 选择掺杂剂的导电类型与源极和漏极掺杂剂的导电类型相反。 注入的掺杂剂在应变硅层的突出部分中增加栅极端部之下的阈值电压Vt，使得其大致等于或大于MOSFET的其余部分的阈值电压。 所产生的应变硅MOSFET在栅极端部下方表现出减小的漏电流。

公开(公告)号：US06878592B1

公开(公告)日：2005-04-12

申请号：US10341772

申请日：2003-01-14

申请人： Paul R. Besser ,  Minh V. Ngo ,  Qi Xiang ,  Eric N. Paton

发明人： Paul R. Besser ,  Minh V. Ngo ,  Qi Xiang ,  Eric N. Paton

IPC分类号： H01L21/20 ,  H01L21/285 ,  H01L21/336 ,  H01L29/51 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L21/28052 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7845

摘要： A transistor architecture utilizes a raised source and drain region to reduce the adverse affects of germanium on silicide regions. Epitaxial growth can form a silicide region above the source and drain. The protocol can utilize any number of silicidation processes. The protocol allows better silicidation in SMOS devices.

摘要翻译： 晶体管架构利用升高的源极和漏极区域来减少锗对硅化物区域的不利影响。 外延生长可以在源极和漏极之上形成硅化物区域。 该协议可以利用任何数量的硅化工艺。 该协议允许在SMOS器件中更好的硅化。

公开(公告)号：US06849527B1

公开(公告)日：2005-02-01

申请号：US10684727

申请日：2003-10-14

申请人： Qi Xiang

发明人： Qi Xiang

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/425

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/6656

摘要： The mobility enhancement of a strained silicon layer is augmented through incorporation of carbon into a strained silicon lattice to which strain is also imparted by an underlying silicon germanium layer. The presence of the relatively small carbon atoms effectively increases the spacing within the strained silicon lattice and thus imparts additional strain. This enhancement may be implemented for any MOSFET device including silicon on insulator MOSFETs, and is preferably selectively implemented for the PMOS components of CMOS devices to achieve approximately equal carrier mobility for the PMOS and NMOS devices.

摘要翻译： 应变硅层的迁移率增强通过将碳并入应变硅晶格中而得到增强，应变也由下层硅锗层施加。 相对较小碳原子的存在有效地增加了应变硅晶格内的间距，从而增加了应变。 可以对包括绝缘体上硅MOSFET的任何MOSFET器件实现该增强，并且优选地针对CMOS器件的PMOS部件选择性地实现，以实现用于PMOS和NMOS器件的大致相等的载流子迁移率。