中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

218 records (took 0.025 seconds)

    Integrated circuits with asymmetric and stacked transistors
    2.
    发明授权
    Integrated circuits with asymmetric and stacked transistors 有权
    具有不对称和堆叠晶体管的集成电路

    公开(公告)号：US08482963B1

    公开(公告)日：2013-07-09

    申请号：US12629831

    申请日：2009-12-02

    Applicant: Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

    Inventor： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

    IPC: G11C11/00

    CPC classification number: G11C11/412

    Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

    Abstract translation: 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

    Field effect transistor having increased carrier mobility
    3.
    发明授权
    Field effect transistor having increased carrier mobility 有权
    场效应晶体管的载流子迁移率增加

    公开(公告)号：US07923785B2

    公开(公告)日：2011-04-12

    申请号：US10643461

    申请日：2003-08-18

    Applicant: Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

    Inventor： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

    IPC: H01L21/336

    CPC classification number: H01L29/4983 ,  H01L29/02 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/78 ,  H01L29/7845 ,  Y10S438/938

    Abstract: According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

    Abstract translation: 根据一个示例性实施例，位于衬底上方的FET包括位于衬底中的通道。 FET还包括位于沟道上方的第一栅极电介质，其中第一栅极电介质具有第一热膨胀系数。 FET还包括位于第一栅极电介质上方的第一栅电极，其中第一栅电极具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一热膨胀系数，从而导致 增加FET中的载流子迁移率。 例如，第二热膨胀系数可以大于第一热膨胀系数。 载流子迁移率的增加可以由例如在通道中产生的拉伸应变引起。

    Method of fabricating an integrated circuit channel region
    6.
    发明授权
    Method of fabricating an integrated circuit channel region 有权
    制造集成电路通道区域的方法

    公开(公告)号：US07138302B2

    公开(公告)日：2006-11-21

    申请号：US10755763

    申请日：2004-01-12

    Applicant: Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

    Inventor： Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

    IPC: H01L21/335 ,  H01L21/84 ,  H01L21/338 ,  H01L21/8249 ,  H01L27/01

    CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7842

    Abstract: An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer above an insulating layer, providing a trench in the compound semiconductor layer, and providing a strained semiconductor layer above the compound semiconductor layer and within the trench. The method can also include removing the strained semiconductor layer from above the compound semiconductor layer, thereby leaving the strained semiconductor layer within the trench and removing the compound semiconductor layer to leave the strained semiconductor layer and form the fin-shaped channel region.

    Abstract translation: 示例性实施例涉及FinFET沟道结构形成的方法。 该方法可以包括在绝缘层之上提供化合物半导体层，在化合物半导体层中提供沟槽，并在化合物半导体层之上和沟槽内提供应变半导体层。 该方法还可以包括从化合物半导体层上方去除应变半导体层，从而将应变半导体层留在沟槽内，并去除化合物半导体层以留下应变半导体层并形成鳍状沟道区。

    Method of fabricating a strained silicon channel FinFET
    9.
    发明申请
    Method of fabricating a strained silicon channel FinFET 有权
    制造应变硅沟道FinFET的方法

    公开(公告)号：US20050153486A1

    公开(公告)日：2005-07-14

    申请号：US10755763

    申请日：2004-01-12

    Applicant: Qi Xiang ,  James Pan ,  Jung-Suk Goo

    Inventor： Qi Xiang ,  James Pan ,  Jung-Suk Goo

    IPC: H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L21/8234

    CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7842

    Abstract: An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer above an insulating layer, providing a trench in the compound semiconductor layer, and providing a strained semiconductor layer above the compound semiconductor layer and within the trench. The method can also include removing the strained semiconductor layer from above the compound semiconductor layer, thereby leaving the strained semiconductor layer within the trench and removing the compound semiconductor layer to leave the strained semiconductor layer and form the fin-shaped channel region.

    Abstract translation: 示例性实施例涉及FinFET沟道结构形成的方法。 该方法可以包括在绝缘层之上提供化合物半导体层，在化合物半导体层中提供沟槽，并在化合物半导体层之上和沟槽内提供应变半导体层。 该方法还可以包括从化合物半导体层上方去除应变半导体层，从而将应变半导体层留在沟槽内，并去除化合物半导体层以留下应变半导体层并形成鳍状沟道区。

Patent Agency Ranking