公开(公告)号：US06381721B1

公开(公告)日：2002-04-30

申请号：US09311990

申请日：1999-05-14

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R3128

CPC classification number: G06F11/0763 ,  G01R31/31855

Abstract: An integrated circuit provides for a connection port having a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, and a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins. The test access port controller is connectable to the test logic in a first mode of operation to effect communication of serial test data under control of an incoming clock signal and is operable in a second mode of operation to communication data as a sequence of serial bits according to a predetermined protocol between the connection port and the on-chip functional circuitry. The integrated circuit includes an error detection circuit for detecting an error condition in the protocol and gating circuitry responsive to detection of the error condition to prevent communication of subsequent data until the error condition is detected as having been removed.

Abstract translation: 集成电路为具有串行数据输入引脚和串行数据输出引脚，片上功能电路和测试逻辑的连接端口提供连接，以及测试访问端口控制器，连接用于通过所述输入端通过芯片边界实现串行数据的通信 和输出引脚。 测试访问端口控制器可以在第一操作模式下连接到测试逻辑，以在输入时钟信号的控制下实现串行测试数据的通信，并且可以在第二操作模式中操作以通信数据作为串行位序列 到连接端口和片上功能电路之间的预定协议。 集成电路包括用于检测协议中的错误状况和门控电路的错误检测电路，其响应于错误状况的检测，以防止后续数据的通信，直到检测到错误状态已被去除。

公开(公告)号：US06178525B1

公开(公告)日：2001-01-23

申请号：US09027870

申请日：1998-02-23

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F1113

CPC classification number: G06F11/3466 ,  G06F11/348

Abstract: There is disclosed a single chip integrated circuit device including on-chip functional circuitry and a plurality of diagnostic units connected to monitor the on-chip functional circuitry. The plurality of diagnostic units detect respective trigger conditions by comparing signals from the on-chip functional circuitry with data held in respective diagnostic registers of the diagnostic units. The single chip integrated circuit device further includes trigger sequence control circuitry arranged to receive the trigger conditions and to initiate a trigger message when a predetermined sequence of the trigger conditions is detected. There is also disclosed a method of controlling such trigger sequences.

Abstract translation: 公开了一种单芯片集成电路装置，其包括片上功能电路和连接到监视片上功能电路的多个诊断单元。 多个诊断单元通过将来自片上功能电路的信号与保存在诊断单元的相应诊断寄存器中的数据进行比较来检测相应的触发条件。 单芯片集成电路装置还包括触发顺序控制电路，其布置成接收触发条件，并且当检测到触发条件的预定序列时发起触发消息。 还公开了一种控制这种触发序列的方法。

公开(公告)号：US6125416A

公开(公告)日：2000-09-26

申请号：US960757

申请日：1997-10-29

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F11/22 ,  G01R31/3185 ,  G06F11/36 ,  G06F15/17

CPC classification number: G06F11/3656 ,  G01R31/318572

Abstract: A single chip integrated circuit device includes a bus system for effecting communication of parallel data on chip, functional circuitry connected to the bus system for executing an operation in response to parallel data received from the bus system, an external port, and a serial to parallel data packet converter interconnecting the parallel bus system and the external port. The external port includes a serial data input connector and a serial data output connector for supplying serial data packets between an external device and the integrated circuit device. The serial data packets each include a packet identifier indicating the length of the data packet and information defining an operation to be executed by the functional circuitry. The serial to parallel data packet converter is operable to read the packet identifier to determine the length of serial packets which are input through the port and to convert them into parallel data for supply in a forward direction to the bus system, such that if the serial data packet has a length which exceeds the bus width, the serial data packet is converted into successive sets of parallel data and placed sequentially on the bus system. The serial to parallel converter further includes flow control logic for indicating that it is ready to receive a subsequent data packet by transmitting a flow control signal in the reverse direction, and for requesting access to the bus system when the parallel data is ready to be output to the functional circuitry. In this device, the serial to parallel conversion of the serial packets into parallel data is effected without involving the functional circuitry, and the parallel data causes the functional circuitry to execute an operation dependent on the information contained in the serial packets from which it has been converted.

Abstract translation: 单芯片集成电路装置包括用于实现芯片上并行数据通信的总线系统，连接到总线系统的功能电路，用于响应从总线系统接收的并行数据执行操作，外部端口和串行到并行 数据包转换器将并行总线系统和外部端口互连。 外部端口包括串行数据输入连接器和串行数据输出连接器，用于在外部设备和集成电路设备之间提供串行数据包。 串行数据分组各自包括指示数据分组的长度的分组标识符和定义要由功能电路执行的操作的信息。 串行到并行数据分组转换器可操作以读取分组标识符以确定通过端口输入的串行分组的长度并将其转换为并行数据，以向前向方向供应到总线系统，使得如果串行 数据包的长度超过总线宽度，串行数据包被转换成连续的并行数据集，并且顺序放置在总线系统上。 串行到并行转换器还包括流控制逻辑，用于指示其准备好通过在相反方向上发送流控制信号来接收后续数据分组，并且当并行数据准备输出时请求对总线系统的访问 到功能电路。 在该装置中，将串行分组串行到并行转换成并行数据，而不涉及功能电路，并行数据使功能电路根据包含在已经被串行数据包的串行数据包中的信息执行操作 转换

公开(公告)号：US20120009778A1

公开(公告)日：2012-01-12

申请号：US13236532

申请日：2011-09-19

Applicant: Robert Warren

Inventor： Robert Warren

IPC: H01L21/768

CPC classification number: G01L1/146 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2201/0264 ,  G01D5/24 ,  G01L9/0072 ,  G01P15/08 ,  G01P15/0975

Abstract: A micro electro-mechanical sensor is provided. The micro electro-mechanical sensor includes a substrate, and a conducting plane disposed on the substrate. A conducting via is disposed on the substrate, such as adjacent to the conducting plane. A plurality of ribbon conductors are disposed over the conducting plane and electrically connected to the conducting via, such that the plurality of ribbon conductors form a transducer array in combination with the conducting plane, such as through capacitive coupling that changes in response to changes in the physical shape of the plurality of ribbons.

Abstract translation: 提供了微机电传感器。 微电子机械传感器包括基板和设置在基板上的导电平面。 导电通孔设置在基板上，例如与导电平面相邻。 多个带状导体设置在导电平面上并电连接到导电通孔，使得多个带状导体与导电平面组合形成换能器阵列，例如通过电容耦合，其响应于 多个色带的物理形状。

公开(公告)号：US20090250227A1

公开(公告)日：2009-10-08

申请号：US12061243

申请日：2008-04-02

Applicant: Clifford D. Brown ,  Robert Warren ,  Lee Smith

Inventor： Clifford D. Brown ,  Robert Warren ,  Lee Smith

IPC: E21B33/13

CPC classification number: E21B43/123 ,  E21B33/10 ,  E21B33/13

Abstract: Plugging a side pocket mandrel using a swelling plug. A system for plugging a port in a side pocket of a mandrel in a subterranean well includes a plugging device installed in the side pocket of the mandrel, the plugging device including a swellable seal material, whereby the seal material swells at least after installation of the plugging device in the side pocket to thereby prevent fluid transfer through the port. A method of plugging a port in a side pocket of a mandrel in a subterranean well includes the steps of: providing the plugging device with a swellable seal material; installing the plugging device in the side pocket; and the seal material swelling in the side pocket, thereby preventing fluid transfer through the port.

Abstract translation: 使用膨胀塞堵塞侧袋心轴。 用于堵塞位于地下井中的心轴的侧袋中的端口的系统包括安装在心轴的侧袋中的堵塞装置，所述堵塞装置包括可膨胀的密封材料，由此密封材料至少在安装之后膨胀 堵塞装置在侧袋中，从而防止流体通过端口传递。 将地下井中心轴的侧袋中的端口堵塞的方法包括以下步骤：为堵塞装置提供可膨胀的密封材料; 将封堵装置安装在侧袋中; 并且密封材料在侧袋中膨胀，从而防止流体通过端口传递。

公开(公告)号：US20090236677A1

公开(公告)日：2009-09-24

申请号：US12054169

申请日：2008-03-24

Applicant: Robert Warren

Inventor： Robert Warren

IPC: H01L29/84 ,  H01L21/00

CPC classification number: G01L1/146 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2201/0264 ,  G01D5/24 ,  G01L9/0072 ,  G01P15/08 ,  G01P15/0975

Abstract: A micro electro-mechanical sensor is provided. The micro electro-mechanical sensor includes a substrate, and a conducting plane disposed on the substrate. A conducting via is disposed on the substrate, such as adjacent to the conducting plane. A plurality of ribbon conductors are disposed over the conducting plane and electrically connected to the conducting via, such that the plurality of ribbon conductors form a transducer array in combination with the conducting plane, such as through capacitive coupling that changes in response to changes in the physical shape of the plurality of ribbons.

Abstract translation: 提供了微机电传感器。 微电子机械传感器包括基板和设置在基板上的导电平面。 导电通孔设置在基板上，例如与导电平面相邻。 多个带状导体设置在导电平面上并电连接到导电通孔，使得多个带状导体与导电平面组合形成换能器阵列，例如通过电容耦合，其响应于 多个色带的物理形状。

公开(公告)号：US07398440B2

公开(公告)日：2008-07-08

申请号：US11015748

申请日：2004-12-17

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28

CPC classification number: G01R31/318536 ,  G01R31/318563

Abstract: An integrated circuit comprising: a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test signals; and a multiplexer between the at least one test input and the test control circuitry, the multiplexer having a least one control input whereby the multiplexer is controllable to direct test signals to one of the plurality of portions.

Abstract translation: 一种集成电路，包括：多个部分，每个部分包括测试控制电路; 至少一个测试输入被布置成接收测试信号; 以及在所述至少一个测试输入和所述测试控制电路之间的多路复用器，所述多路复用器具有至少一个控制输入，由此所述多路复用器被控制以将测试信号引导到所述多个部分中的一个。

公开(公告)号：US20070268990A1

公开(公告)日：2007-11-22

申请号：US11635384

申请日：2006-12-07

Applicant: Robert Warren

Inventor： Robert Warren

IPC: H04L7/00

CPC classification number: H04L7/0337

Abstract: Circuitry for synchronizing communications between clock environments wherein a change of state is transmitted from a first clock environment to a second clock environment, the first clock environment being timed by a first clock signal and the second clock environment being timed by a second clock signal, the first and second clock signals having nominally the same frequency but an unknown phase relationship, the circuitry comprising: delay means in the first clock environment arranged to generate a plurality of timing signals by delaying said first clock signal by respectively different delay values; sampling means in the second clock environment for sampling said plurality of timing signals at timing determined by said second clock signal thereby generating a plurality of sampled timing signals; and determining means for generating a control signal based on said plurality of sampled timing signals and outputting said control signal for controlling the transfer time of said change of state.

Abstract translation: 电路，用于在其中将状态改变从第一时钟环境传输到第二时钟环境的时钟环境之间进行通信，所述第一时钟环境由第一时钟信号定时，并且所述第二时钟环境由第二时钟信号定时， 第一和第二时钟信号具有名义上相同的频率但是未知的相位关系，所述电路包括：第一时钟环境中的延迟装置，被布置成通过分别延迟所述第一时钟信号分别不同的延迟值来产生多个定时信号; 在第二时钟环境中的采样装置，用于在由所述第二时钟信号确定的定时采样所述多个定时信号从而产生多个采样的定时信号; 以及确定装置，用于基于所述多个采样定时信号产生控制信号，并输出所述控制信号以控制所述状态改变的传送时间。

公开(公告)号：US20070241440A1

公开(公告)日：2007-10-18

申请号：US11499285

申请日：2006-08-04

Applicant: Dinhphuoc Hoang ,  Thomas Noll ,  Anil Agarwal ,  Robert Warren ,  Matthew Read ,  Anthony LoBianco

Inventor： Dinhphuoc Hoang ,  Thomas Noll ,  Anil Agarwal ,  Robert Warren ,  Matthew Read ,  Anthony LoBianco

IPC: H01L23/49

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  Y10T29/49126 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component.

Abstract translation: 根据一个示例性实施例，包覆成型的包装包括位于基底上的部件。 包覆成型的包装进一步包括位于组件和衬底之上的包覆成型。 包覆成型的包装还包括位于衬底上方和覆盖模制件中的引线键合框架，其中引线键合框架围绕组件，并且其中引线键合框架包括多个引线键。 引线键盘在组件周围形成EMI屏蔽。 根据该示例性实施例，包覆成型的封装还包括位于包覆模制体的顶表面上并连接到引线键合框架的导电层，其中导电层在部件上形成EMI屏蔽。

公开(公告)号：US07159199B2

公开(公告)日：2007-01-02

申请号：US10816799

申请日：2004-04-02

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: The present invention is directed to methods for verifying adequate synchronization of signals that cross clock environments. According to one exemplary method, a circuit under design includes a plurality of functional elements and a plurality of clock environments, and has one or more signals passing from one clock environment to another therein. The method includes the steps of (i) modelling at least one of the functional elements to have an unknown state as an output for a predetermined time after a timing event of a clock signal, (ii) simulating the circuit, and (iii) determining which functional element is a synchronizer to thereby identify if there is a synchronization problem for a signal passing from one clock environment to another.

Abstract translation: 本发明涉及用于验证跨时钟环境的信号的充分同步的方法。 根据一个示例性方法，设计中的电路包括多个功能元件和多个时钟环境，并且具有从一个时钟环境到另一个时钟环境的一个或多个信号。 该方法包括以下步骤：（i）在时钟信号的定时事件，（ii）模拟电路之后的预定时间内将功能元件中的至少一个功能元件建模为具有未知状态作为输出，以及（iii）确定 哪个功能元件是同步器，从而识别对于从一个时钟环境到另一个时钟环境的信号是否存在同步问题。