公开(公告)号：US11342033B1

公开(公告)日：2022-05-24

申请号：US17135467

申请日：2020-12-28

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Deepanshu Dutta ,  Huai-yuan Tseng

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56

Abstract: A storage device is disclosed. The storage device is configured to: determine data states for a first set of memory cells of a first neighboring word line of the and a second set of memory cells of a second neighboring word line, the first and the second neighboring word lines being adjacent to a selected word line; identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, each zone of the plurality of zones corresponding to a data retention compensation scheme; and perform a read operation on the selected word line including applying each data retention compensation scheme corresponding to any zones identified.

公开(公告)号：US11302409B2

公开(公告)日：2022-04-12

申请号：US16854030

申请日：2020-04-21

Applicant: SanDisk Technologies LLC

Inventor： Xue Pitner ,  Deepanshu Dutta ,  Huai-Yuan Tseng ,  Ravi Kumar ,  Cynthia Hsu

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.

公开(公告)号：US20210405891A1

公开(公告)日：2021-12-30

申请号：US16916620

申请日：2020-06-30

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G06F3/06

Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.

公开(公告)号：US20210383870A1

公开(公告)日：2021-12-09

申请号：US16892753

申请日：2020-06-04

Applicant: SanDisk Technologies LLC

Inventor： Huai-Yuan Tseng ,  Henry Chin ,  Deepanshu Dutta

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array relative to an outer memory string group of a set of memory string groups.

公开(公告)号：US20210241836A1

公开(公告)日：2021-08-05

申请号：US16778821

申请日：2020-01-31

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C5/06 ,  G11C16/10 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/02

Abstract: Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with operations of sense circuits in updating their latches based on results from a verify test in a previous program loop. For an intermediate set of program loops, the overlap is avoided. The ramp up rate can be larger and the transition voltage smaller for the initial and final sets of program loops compared to the intermediate set of program loops.

公开(公告)号：US11017869B2

公开(公告)日：2021-05-25

申请号：US16893626

申请日：2020-06-05

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/06 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.

公开(公告)号：US10930355B2

公开(公告)日：2021-02-23

申请号：US16432142

申请日：2019-06-05

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/24 ,  G11C16/08 ,  G11C16/34 ,  G11C16/32

Abstract: A methodology and structure for accounting for fabrication difference in memory holes is described. Increasing the distance of the memory holes from the sources of etchant or other fabrication material results in different characteristics of the memory from the outer memory holes to the inner memory holes. These difference can be accounted for by grouping the memory holes and altering the parameters of the program or verify operations based on the groupings. The bitline voltage for the inner grouping can be less than the bitline voltage for the outer groupings. The sense timing can be greater for the outer groupings relative to the inner groupings. This can result in voltage threshold for the inner groupings and outer groupings overlying each other to improve memory performance.

公开(公告)号：US10861537B1

公开(公告)日：2020-12-08

申请号：US16668886

申请日：2019-10-30

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Abhijith Prakash

IPC: G11C11/56 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/408

Abstract: Techniques are provided for operating non-volatile storage. Peak current consumption may be reduced in connection with sensing non-volatile memory cells. Peak current consumption may be reduced when a first read condition is present. In one aspect, the value of a parameter of a voltage that is applied to a word line during a pre-read phase of a sense operation is controlled in order to reduce peak current consumption when the first read condition is present. Examples of the parameter include a ramp rate, a number of intermediate voltage levels, and a start time.

公开(公告)号：US10559370B2

公开(公告)日：2020-02-11

申请号：US15928976

申请日：2018-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Piyush Dak ,  Wei Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Mohan Dunga

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56 ,  G11C16/04

Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programming operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.

公开(公告)号：US10559365B2

公开(公告)日：2020-02-11

申请号：US15937420

申请日：2018-03-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11524 ,  H01L29/08 ,  H01L29/10

Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a bias variance state associated with the plurality of control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.