Method and Device for Generating an Adjustable Bandgap Reference Voltage
    51.
    发明申请
    Method and Device for Generating an Adjustable Bandgap Reference Voltage 审中-公开
    用于产生可调带隙参考电压的方法和装置

    公开(公告)号:US20160357213A1

    公开(公告)日:2016-12-08

    申请号:US15243556

    申请日:2016-08-22

    CPC classification number: G05F3/267 G05F1/468 G05F3/30

    Abstract: A circuit includes a first PMOS transistor that includes a first PMOS source coupled to a first input node, a first PMOS gate, and a first PMOS drain. A second PMOS transistor includes a second PMOS source coupled to a second input node, a second PMOS gate, and a second PMOS drain coupled to the second PMOS gate. A first resistor coupled between the first PMOS source and a ground node. A first diode element coupled between the first resistor and the ground node and a second diode element coupled between the second PMOS source and the ground node. A third PMOS transistor includes a third PMOS gate, a third PMOS source coupled to a supply node, and a third PMOS drain coupled to the first input node. A fourth PMOS transistor includes a fourth PMOS gate coupled to the third PMOS gate, a fourth PMOS source coupled to the supply node, and a fourth PMOS drain coupled to the second input node.

    Abstract translation: 电路包括第一PMOS晶体管,其包括耦合到第一输入节点的第一PMOS源极,第一PMOS栅极和第一PMOS漏极。 第二PMOS晶体管包括耦合到第二输入节点的第二PMOS源极,第二PMOS栅极和耦合到第二PMOS栅极的第二PMOS漏极。 耦合在第一PMOS源极和接地节点之间的第一电阻器。 耦合在第一电阻器和接地节点之间的第一二极管元件和耦合在第二PMOS源极和接地节点之间的第二二极管元件。 第三PMOS晶体管包括第三PMOS栅极,耦合到电源节点的第三PMOS源极和耦合到第一输入节点的第三PMOS漏极。 第四PMOS晶体管包括耦合到第三PMOS栅极的第四PMOS栅极,耦合到电源节点的第四PMOS源极和耦合到第二输入节点的第四PMOS漏极。

    Regulator with Low Dropout Voltage and Improved Stability

    公开(公告)号:US20160062377A1

    公开(公告)日:2016-03-03

    申请号:US14937671

    申请日:2015-11-10

    CPC classification number: G05F1/575 H03F3/45179

    Abstract: The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node.

    REGULATOR FOR INTEGRATED CIRCUIT
    55.
    发明申请
    REGULATOR FOR INTEGRATED CIRCUIT 有权
    集成电路调节器

    公开(公告)号:US20150001938A1

    公开(公告)日:2015-01-01

    申请号:US14315989

    申请日:2014-06-26

    Inventor: Jimmy Fort

    CPC classification number: H02M1/08 G06F21/755 Y10T307/549

    Abstract: An electronic circuit includes a functional circuit in series with at least one first current source between two terminals of application of a power supply voltage. The first current source is controllable between an operating mode where it delivers a fixed current, independent from the power consumption of said functional circuit, and an operating mode where it delivers a variable current, depending on the power consumption of the functional circuit.

    Abstract translation: 电子电路包括与施加电源电压的两个端子之间的至少一个第一电流源串联的功能电路。 第一电流源可以在其提供固定电流的操作模式之间是可控的,独立于所述功能电路的功耗,以及根据功能电路的功耗而传送可变电流的操作模式。

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