公开(公告)号：US09076691B2

公开(公告)日：2015-07-07

申请号：US13875722

申请日：2013-05-02

Applicant: Samsung Display Co., Ltd.

Inventor： Shin Il Choi ,  Sang Gab Kim ,  Su Bin Bae ,  Yu-Gwang Jeong

IPC: H01L21/00 ,  H01L27/12 ,  H01L27/32

CPC classification number: H01L27/124 ,  H01L27/1248 ,  H01L27/322 ,  H01L27/3248

Abstract: A method of manufacturing a thin film transistor array panel includes: a gate insulating layer disposed on a gate electrode, a semiconductor disposed on the gate insulating layer, a source electrode opposite a drain electrode disposed on the semiconductor, a color filter disposed on the gate insulating layer, an overcoat disposed on the color filter and including an inorganic material. A first dry etching is performed using the photosensitive film pattern as a mask to etch the overcoat and provide a preliminary contact hole, through which a portion of the color filter is exposed. A second dry etching is performed using the overcoat as a mask to etch the color filter through the preliminary contact hole and to provide a contact hole, through which a portion of the drain electrode is exposed. A pixel electrode is connected to the drain electrode through the contact hole, on the overcoat.

Abstract translation: 制造薄膜晶体管阵列面板的方法包括：设置在栅电极上的栅极绝缘层，设置在栅极绝缘层上的半导体，设置在半导体上的漏电极相对的源电极，设置在栅极上的滤色器 绝缘层，设置在滤色器上并包括无机材料的外涂层。 使用感光膜图案作为掩模进行第一干蚀刻，以蚀刻外涂层并提供初步接触孔，滤色片的一部分穿过该预接触孔。 使用外涂层作为掩模进行第二干蚀刻，以通过预接触孔蚀刻滤色器，并提供接触孔，漏电极的一部分暴露在该接触孔中。 像素电极通过外罩上的接触孔连接到漏电极。

公开(公告)号：US20150072484A1

公开(公告)日：2015-03-12

申请号：US14487300

申请日：2014-09-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ji-Young Park ,  Yu-Gwang Jeong ,  Sang Gab Kim ,  Joon Geol Lee

IPC: H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1259 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

Abstract translation: 薄膜晶体管阵列面板包括基板，栅极线，每个栅极线包括栅极焊盘，栅极绝缘层，数据线，每条数据线包括连接到源极和漏极的数据焊盘，设置在数据线上的第一钝化层和 漏电极，第一电场产生电极，设置在第一电场产生电极上的第二钝化层和第二电场产生电极。 栅极绝缘层和第一和第二钝化层包括暴露栅极焊盘的一部分的第一接触孔，第一和第二钝化层包括暴露数据焊盘的一部分的第二接触孔，以及第一和第二钝化层中的至少一个 并且第二接触孔具有在上侧具有比在下侧更宽的面积的正锥形结构。

公开(公告)号：US08940565B1

公开(公告)日：2015-01-27

申请号：US14194015

申请日：2014-02-28

Applicant: Samsung Display Co. Ltd.

Inventor： Ji Young Park ,  Gwan Ha Kim ,  Dong Il Kim ,  Sang Gab Kim

IPC: H01L21/00 ,  H01L27/12

CPC classification number: H01L27/1259 ,  G02F2001/134372

Abstract: A method of manufacturing a thin film transistor array substrate includes providing a plurality of gate lines and a plurality of data lines on a first substrate, providing an organic layer on the gate lines and the data lines, providing a first electrode on the organic layer, providing a passivation layer on the first electrode, providing a second electrode on the passivation layer, providing a first cover layer on the second electrode to cover the second electrode, providing a plurality of photosensitive layer patterns on the first cover layer, providing a plurality of first cutout patterns in the first cover layer and a plurality of second cutout patterns in the second electrode using the photosensitive layer patterns as an etch mask, and providing a plurality of third cutout patterns in the passivation layer using the first cover layer as an etch mask.

Abstract translation: 制造薄膜晶体管阵列基板的方法包括：在第一基板上设置多个栅极线和多个数据线，在栅极线和数据线上提供有机层，在有机层上提供第一电极， 在所述第一电极上提供钝化层，在所述钝化层上提供第二电极，在所述第二电极上提供第一覆盖层以覆盖所述第二电极，在所述第一覆盖层上提供多个感光层图案，提供多个 第一覆盖层中的第一切除图案和使用感光层图案作为蚀刻掩模的第二电极中的多个第二切割图案，并且使用第一覆盖层作为蚀刻掩模在钝化层中提供多个第三切除图案 。

公开(公告)号：US08921852B2

公开(公告)日：2014-12-30

申请号：US13915342

申请日：2013-06-11

Applicant: Samsung Display Co., Ltd.

Inventor： Shin II Choi ,  Sang Gab Kim ,  Hyang-Shik Kong ,  Su Bin Bae ,  Yu-Gwang Jeong

IPC: H01L29/417 ,  H01L29/786 ,  H01L29/12 ,  H01L21/77

CPC classification number: H01L21/77 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a substrate, a gate line positioned on the substrate and including a gate electrode, a semiconductor layer positioned on the substrate and including an oxide semiconductor, a data wire layer positioned on the substrate and including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, and a capping layer covering the data wire layer, in which an end of the capping layer is inwardly recessed as compared to an end of the data wire layer.

Abstract translation: 薄膜晶体管阵列面板包括：衬底，位于衬底上并包括栅电极的栅极线，位于衬底上并包括氧化物半导体的半导体层，位于衬底上的数据线层，包括数据线 与栅极线交叉，连接到数据线的源电极和面对源电极的漏电极和覆盖数据线层的覆盖层，其中封盖层的端部向内凹入，与顶端 数据线层。

公开(公告)号：US20130306974A1

公开(公告)日：2013-11-21

申请号：US13952059

申请日：2013-07-26

Applicant: Samsung Display Co., Ltd.

Inventor： Jeong Min PARK ,  Dong-Won Woo ,  Je Hyeong Park ,  Sang Gab Kim ,  Jung-Soo Lee ,  Ji-Hyun Kim

IPC: H01L29/786

CPC classification number: H01L29/786 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/78645

Abstract: A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.

Abstract translation: 薄膜晶体管阵列板的制造方法包括：使用非过氧化物的蚀刻剂，在基板上同时形成栅极导体和第一电极; 在所述栅极导体和所述第一电极上形成栅极绝缘层; 在栅极绝缘层上形成半导体，源电极和漏电极; 在半导体，源电极和漏电极上形成钝化层; 以及在所述钝化层上形成第二电极层。