公开(公告)号：US20070070701A1

公开(公告)日：2007-03-29

申请号：US11500410

申请日：2006-08-08

申请人： Moo-Sung Kim ,  Young-Ho Lim

发明人： Moo-Sung Kim ,  Young-Ho Lim

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C8/08 ,  G11C16/0483

摘要： A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating a program voltage to be supplied to the memory cell; and a program voltage controller controlling a start level of the program voltage. The device supplies an LSB start voltage to a selected word line during an LSB program, and an MSB start voltage higher than the LSB start voltage to the selected word line during an MSB program.

摘要翻译： 提供一种能够在多级单元编程操作期间提高编程速度的NAND快闪存储器件及其编程方法。 该设备使用ISPP方法执行编程操作。 另外，该设备包括存储多位数据的存储单元; 编程电压产生电路，产生要提供给存储单元的编程电压; 以及控制编程电压的起始电平的编程电压控制器。 在MSB程序期间，器件在LSB程序期间将LSB起始电压提供给所选择的字线，并在MSB程序期间向所选字线提供高于LSB起始电压的MSB启动电压。

公开(公告)号：US06804150B2

公开(公告)日：2004-10-12

申请号：US10236585

申请日：2002-09-06

申请人： Jung-Hoon Park ,  Young-Ho Lim ,  Hyoung-Gon Kim

发明人： Jung-Hoon Park ,  Young-Ho Lim ,  Hyoung-Gon Kim

IPC分类号： G11C1604

CPC分类号： G11C16/08 ,  G11C16/12

摘要： A non-volatile integrated circuit NAND type flash memory device is provided that includes a select line driver and a slope control circuit. The select line driver supplies a string select line with a select voltage limited below a power supply voltage while a program voltage is supplied to a word line. The slope control circuit controls a rising slope of the program voltage such that a capacitive coupling does not arise between the string select line and a selected word line during a program operation. At this time, the select voltage that the select line driver supplies into the string select line is lower than the power supply voltage, and a difference between the select voltage and the power supply voltage is at least as much as a coupling voltage between the string select line and the selected word line. In addition, the program voltage that the slope control circuit supplies into the selected word line can be increased in a staircase form during the program operation.

摘要翻译： 提供了包括选择线驱动器和斜率控制电路的非易失性集成电路NAND型闪速存储器件。 选择线驱动器提供选择电压限制在电源电压以下的字符串选择线，而编程电压被提供给字线。 斜率控制电路控制编程电压的上升斜率，使得在编程操作期间在串选择线和选定字线之间不产生电容耦合。 此时，选择线驱动器提供给串选择线的选择电压低于电源电压，并且选择电压和电源电压之间的差异至少等于串之间的耦合电压 选择行和所选字线。 此外，斜坡控制电路提供给所选字线的编程电压可以在编程操作期间以阶梯形式增加。

公开(公告)号：US06704239B2

公开(公告)日：2004-03-09

申请号：US09997533

申请日：2001-11-29

申请人： Tae-Hee Cho ,  Young-Ho Lim

发明人： Tae-Hee Cho ,  Young-Ho Lim

IPC分类号： G11C700

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/12 ,  G11C16/26 ,  G11C2207/2245

摘要： A non-volatile semiconductor memory device includes a plurality of page buffers, each corresponding to a sense node. Voltages of a first set of sense nodes are varied according to states of corresponding memory cells during a first sense period, while voltages of a second set of sense nodes are fixed at a predetermined voltage. During the second sense period, voltages of the second set of sense nodes are varied according to states of corresponding memory cells, while voltages of the first set of sense nodes are fixed at a predetermined voltage. Using this sensing scheme, even though a sense node corresponding to an OFF cell is floated, a voltage of the floated sense node is not coupled down when a voltage of a neighboring sense node corresponding to an ON cell is lowered.

公开(公告)号：US06545910B2

公开(公告)日：2003-04-08

申请号：US09982316

申请日：2001-10-18

申请人： Dae-Seok Byeon ,  Heung-Soo Im ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Heung-Soo Im ,  Young-Ho Lim

IPC分类号： G11C1604

CPC分类号： G11C29/02

摘要： Disclosed is a non-volatile semiconductor memory device provided therein.with a word line defect check circuit. The non-volatile semiconductor memory device includes: a memory cell array including a plurality of cell array blocks including a plurality of cell strings that consist of floating gate memory cell transistors that its drain-source channels are in series connected each other between string select transistors and ground select transistors and that its control gates are correspondingly connected to a plurality of word lines, and a word line short check circuit that inputs different levels of voltage to each of the plurality of word lines that is adjacent from one another during a predetermined charging time, and that generates a short sense signal that indicates whether short between adjacent word lines is occurred by checking voltage levels of the word lines that were supplied with a same level of voltage, after the charging time is lapsed by a predetermined time.

摘要翻译： 公开了一种使用字线缺陷检查电路设置在其中的非易失性半导体存储器件。 非易失性半导体存储器件包括：包括多个单元阵列块的存储单元阵列，所述多个单元阵列块包括由浮置栅极存储单元晶体管组成的多个单元串，所述浮栅存储单元晶体管的漏源通道在串选择晶体管之间串联连接 和地选择晶体管，并且其控制栅极对应地连接到多个字线，以及字线短路检查电路，其在预定充电期间彼此相邻的多个字线中的每一个输入不同电平的电压 并且在充电时间经过预定时间之后，通过检查提供有相同电平电平的字线的电压电平，产生指示相邻字线之间是否发生短路的短路检测信号。

公开(公告)号：US5617353A

公开(公告)日：1997-04-01

申请号：US658438

申请日：1996-06-05

申请人： Young-Ho Lim ,  Kang-Deog Suh

发明人： Young-Ho Lim ,  Kang-Deog Suh

IPC分类号： G11C17/00 ,  G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C11/40

CPC分类号： G11C16/08 ,  G11C16/0483

摘要： The present invention provides an electrically erasable and programmable nonvolatile semiconductor memory device (EEPROM) with NAND structured cells which is capable of reducing the number of peripheral circuits required to drive each memory block. The EEPROM according to the present invention includes memory blocks having transfer transistors controlled by a memory block selection signal, wherein the transfer transistors serve as a path through which control gate driving signals are supplied, and wherein control gate driving signals are applied to word lines at full voltage due to a self-boosting operation of each transfer transistor.

公开(公告)号：US08085589B2

公开(公告)日：2011-12-27

申请号：US12881321

申请日：2010-09-14

申请人： Moo-Sung Kim ,  Young-Ho Lim

发明人： Moo-Sung Kim ,  Young-Ho Lim

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/10 ,  G11C16/3427

摘要： A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the selected word line to a third voltage after programming the memory cells connected to the selected word line, the third voltage being lower than the first voltage, and recovering a fourth voltage of the selected word line and the non-selected word lines, the fourth voltage being lower than the second and third voltages.

摘要翻译： 一种对闪存进行编程的方法包括通过向所选择的字线施加第一电压并将第二电压施加到未选择的字线来连接到所选字线的编程存储单元，所述第二电压低于所述第一电压， 在对连接到所选字线的存储单元进行编程之后，所选字线的第一电压为第三电压，第三电压低于第一电压，并且恢复所选字线和未选字线的第四电压 ，第四电压低于第二和第三电压。

公开(公告)号：US08045380B2

公开(公告)日：2011-10-25

申请号：US12939251

申请日：2010-11-04

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.

摘要翻译： 闪速存储器和闪速存储器的编程方法包括对字线施加通过电压以升高被释放到接地电压的通道电压。 一个编程电压被施加到所选择的字线，并且当编程电压被施加到所选择的字线时，局部电压被施加到提供有通过电压的至少一个字线。 局部电压低于通过电压，等于或高于接地电压。 在将编程电压施加到所选择的字线之前，升压的通道电压可以被放电。

公开(公告)号：US07974125B2

公开(公告)日：2011-07-05

申请号：US12822246

申请日：2010-06-24

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C8/10 ,  G11C8/12 ,  G11C29/806 ,  G11C29/844

摘要： A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.

摘要翻译： 闪速存储器件包括多个存储器块，被配置为响应于块选择信号来选择至少一个存储器块的解码器，被配置为响应于块地址产生块选择信号并且产生标志信号的控制器， 块地址对应于坏块，并且输出缓冲器被配置为响应于指示块地址对应于坏块的标志信号输出固定数据。 当块地址对应于坏块时，控制器产生块选择信号以使解码器中断对应于块地址的存储块的选择。

公开(公告)号：US07965558B2

公开(公告)日：2011-06-21

申请号：US12721913

申请日：2010-03-11

申请人： Dong-Hyuk Chae ,  Young-Ho Lim

发明人： Dong-Hyuk Chae ,  Young-Ho Lim

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C16/0483

摘要： Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed.

摘要翻译： 产生用于编程非易失性存储器件的编程电压的方法包括产生初始电压并响应于初始电压产生第一斜变电压。 第一斜坡电压的斜坡速度比初始电压的斜坡速度慢。 响应于第一斜坡电压产生第二斜坡电压。 第二斜坡电压具有比第一斜坡电压更低的纹波。 输出第二斜坡电压作为编程非易失性存储器件的编程电压。 一个编程电压发生电路包括：一个编程电压产生单元，被配置为产生一个初始电压;一个斜坡电路，被配置为产生一个响应初始电压的第一斜坡电压;以及一个电压控制单元，被配置为产生一个具有相对低纹波的第二斜坡电压 并且响应于第一斜坡电压的电压电平而输出第一斜坡电压或第二斜坡电压。 还公开了包括程序电压产生电路的半导体存储器件。

公开(公告)号：US07787306B2

公开(公告)日：2010-08-31

申请号：US12172904

申请日：2008-07-14

申请人： Jung-Hoon Park ,  Sung-Soo Lee ,  Young-Ho Lim ,  Chang-Sub Lee ,  Ki-Tae Park

发明人： Jung-Hoon Park ,  Sung-Soo Lee ,  Young-Ho Lim ,  Chang-Sub Lee ,  Ki-Tae Park

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

摘要： A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is higher than the first voltage thereto, and reading data from a memory cell that is coupled to the selected word line.

摘要翻译： 一种读取闪速存储器件的方法可以包括通过向其施加选择电压来驱动所选择的字线并通过向其施加第一电压来驱动未选择的字线，通过施加第二电压来驱动未选择的字线和第一和第二选择线， 高于其第一电压，并且从耦合到所选字线的存储单元读取数据。