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    Non-volatile semiconductor memory device having word line defect check circuit
    1.
    发明授权
    Non-volatile semiconductor memory device having word line defect check circuit 有权
    具有字线缺陷检查电路的非易失性半导体存储器件

    公开(公告)号：US06545910B2

    公开(公告)日：2003-04-08

    申请号：US09982316

    申请日：2001-10-18

    申请人： Dae-Seok Byeon ,  Heung-Soo Im ,  Young-Ho Lim

    发明人： Dae-Seok Byeon ,  Heung-Soo Im ,  Young-Ho Lim

    IPC分类号： G11C1604

    CPC分类号： G11C29/02

    摘要： Disclosed is a non-volatile semiconductor memory device provided therein.with a word line defect check circuit. The non-volatile semiconductor memory device includes: a memory cell array including a plurality of cell array blocks including a plurality of cell strings that consist of floating gate memory cell transistors that its drain-source channels are in series connected each other between string select transistors and ground select transistors and that its control gates are correspondingly connected to a plurality of word lines, and a word line short check circuit that inputs different levels of voltage to each of the plurality of word lines that is adjacent from one another during a predetermined charging time, and that generates a short sense signal that indicates whether short between adjacent word lines is occurred by checking voltage levels of the word lines that were supplied with a same level of voltage, after the charging time is lapsed by a predetermined time.

    摘要翻译： 公开了一种使用字线缺陷检查电路设置在其中的非易失性半导体存储器件。 非易失性半导体存储器件包括：包括多个单元阵列块的存储单元阵列，所述多个单元阵列块包括由浮置栅极存储单元晶体管组成的多个单元串，所述浮栅存储单元晶体管的漏源通道在串选择晶体管之间串联连接 和地选择晶体管，并且其控制栅极对应地连接到多个字线，以及字线短路检查电路，其在预定充电期间彼此相邻的多个字线中的每一个输入不同电平的电压 并且在充电时间经过预定时间之后，通过检查提供有相同电平电平的字线的电压电平，产生指示相邻字线之间是否发生短路的短路检测信号。

    Current mirror type sense amplifier circuit for semiconductor memory device
    2.
    发明授权
    Current mirror type sense amplifier circuit for semiconductor memory device 有权
    用于半导体存储器件的电流镜型读出放大器电路

    公开(公告)号：US6087859A

    公开(公告)日：2000-07-11

    申请号：US216197

    申请日：1998-12-18

    申请人： Dong-Woo Lee ,  Heung-Soo Im

    发明人： Dong-Woo Lee ,  Heung-Soo Im

    IPC分类号： G11C17/18 ,  G11C7/06 ,  G11C11/407 ,  G11C11/419 ,  G11C16/06

    CPC分类号： G11C7/062 ,  G11C2207/063

    摘要： A sense amplifier circuit includes a first voltage-controlled current source to supply current proportional to a first bias voltage to a reference node and a second voltage-controlled current source to supply current proportional to a second bias voltage to a sensing node. The first and second bias voltages are internally generated in response to an externally applied sense amp control signal. A current mirror circuit is also provided for the sense amplifier circuit. The current mirror circuit commonly deliver current proportional to the voltage level of the reference node to the reference and sensing nodes. A differential amplifier amplifies a difference voltage between reference and sensing nodes. This current mirror type sense amplifier circuit allows data sensing operation to be performed without being influenced from the external conditions and without sensing speed loss due to the instability of the precharge current since the voltage-controlled current sources are controlled by the internal bias voltages.

    摘要翻译： 感测放大器电路包括第一电压控制电流源，以向参考节点提供与第一偏置电压成比例的电流，以及将第二电压控制电流源与第二偏置电压成比例的电流提供给感测节点。 响应于外部施加的感测放大器控制信号，内部产生第一和第二偏置电压。 还为读出放大器电路提供电流镜电路。 电流镜电路通常将与参考节点的电压成比例的电流传递给参考和感测节点。 差分放大器放大参考和感测节点之间的差分电压。 该电流镜式读出放大器电路允许执行数据检测操作而不受外部条件的影响，并且由于由于内部偏置电压来控制压控电流源，所以不会由于预充电电流的不稳定而感测到速度损失。

    Sensing amplifier with current mirror
    5.
    发明授权
    Sensing amplifier with current mirror 失效
    感应放大器带电流镜

    公开(公告)号：US5856748A

    公开(公告)日：1999-01-05

    申请号：US845270

    申请日：1997-04-24

    申请人： Yong-Seok Seo ,  Heung-Soo Im

    发明人： Yong-Seok Seo ,  Heung-Soo Im

    IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  H03F3/45

    CPC分类号： G11C7/062

    摘要： A sense amplifier increases the differential voltage between a reference signal and a sense signal by using a current mirror to control the generation of the reference signal and the sense signal responsive to a common control signal. The sense amplifier includes a reference signal generator for generating the reference signal at a reference node responsive to a reference cell, a sense signal generator for generating the sense signal at a sense node responsive to the state of a memory cell, and a differential amplifier for amplifying the voltage difference between the reference signal and the sense signal. The reference node is coupled to the reference cell which discharges current from the reference node, and the sense node is coupled to the memory cell which discharges current from the sense node. The reference signal generator includes a first current source transistor that is coupled between a power supply terminal and the reference node. The sense signal generator includes a second current source transistor coupled between the power supply terminal and the sense node. The control terminals of the first and second transistors are coupled together to receive the common control signal from either the reference node or the sense node. In either configuration, the control terminal of one of the current source transistor is decoupled from its respective node to allow the voltage of the node to vary widely with respect to the other node.

    摘要翻译： 感测放大器通过使用电流镜来增加参考信号和感测信号之间的差分电压，以响应于公共控制信号来控制参考信号的产生和感测信号。 读出放大器包括：参考信号发生器，用于响应于参考单元在参考节点处产生参考信号;感测信号发生器，用于响应于存储器单元的状态在感测节点处产生感测信号;以及差分放大器， 放大参考信号和感测信号之间的电压差。 参考节点耦合到从参考节点排出电流的参考单元，并且感测节点耦合到从感测节点放电电流的存储器单元。 参考信号发生器包括耦合在电源端子和参考节点之间的第一电流源晶体管。 感测信号发生器包括耦合在电源端子和感测节点之间的第二电流源晶体管。 第一和第二晶体管的控制端子耦合在一起以从参考节点或感测节点接收公共控制信号。 在任一配置中，电流源晶体管之一的控制端与其相应的节点去耦，以允许节点的电压相对于另一个节点变化很大。

    Sense amplifier circuit for use in a semiconductor memory device
    7.
    发明授权
    Sense amplifier circuit for use in a semiconductor memory device 有权
    用于半导体存储器件的感测放大器电路

    公开(公告)号：US06381187B1

    公开(公告)日：2002-04-30

    申请号：US09671465

    申请日：2000-09-27

    申请人： Dong-Woo Lee ,  Heung-Soo Im

    发明人： Dong-Woo Lee ,  Heung-Soo Im

    IPC分类号： G11C700

    CPC分类号： G11C7/062 ,  G11C7/067

    摘要： Disclosed herein is a sense amplifier circuit which includes a first, a second and a third similar load transistors. The first and second load transistors supply a dummy data line with a current of the same amount to one another. Acting in a current mirror configuration, the third load transistor supplies a data line with a current equaling the total current supplied by the first and second load transistors. A dummy memory cell is composed of the same transistor as an on-state memory cell. According to this sense amplifier structure, it is very easy to obtain a dummy cell current which has an intermediate value consistently between an on cell current and an off cell current of the memory cell, which are supplied from the third load transistor to the data line. The improved intermediate value yields a reliable readout of the memory cell.

    摘要翻译： 这里公开了一种读出放大器电路，其包括第一，第二和第三类似的负载晶体管。 第一和第二负载晶体管提供具有彼此相同量的电流的虚拟数据线。 作为电流镜配置，第三负载晶体管以等于由第一和第二负载晶体管提供的总电流的电流提供数据线。 虚拟存储单元由与状态存储单元相同的晶体管组成。 根据这种感测放大器结构，很容易获得在从第三负载晶体管提供到数据线的存储单元的导通单元电流和截止单元电流之间具有一致的中间值的虚设单元电流 。 改进的中间值产生可靠的存储单元的读出。

    Read-only memory device having bit line discharge circuitry and method of reading data from the same
    8.
    发明授权
    Read-only memory device having bit line discharge circuitry and method of reading data from the same 有权
    具有位线放电电路的只读存储器件和从其读取数据的方法

    公开(公告)号：US6018487A

    公开(公告)日：2000-01-25

    申请号：US213721

    申请日：1998-12-17

    申请人： June Lee ,  Heung-Soo Im

    发明人： June Lee ,  Heung-Soo Im

    IPC分类号： G11C11/40 ,  G11C7/12 ,  G11C17/12 ,  G11C7/00

    CPC分类号： G11C17/12 ,  G11C7/12

    摘要： A mask ROM of the invention discharges bit lines selectively before a bit line precharge operation in response to an externally applied command. A column decoder selects one of bit lines in response to column select signals. A discharge control circuit generates a first discharge control signal in response to the command. A discharge predecoder generates a plurality of second discharge control signals by logically combining the first discharge control signal with the column select signals. A bit line discharge circuit selectively discharges the bit lines in response to the second discharge control signals. The mask ROM is free from bit line coupling due to the selection of particular memory cells, the cell selection sequence and the programmed states of the selected cells, leading to an improvement in read speed.

    摘要翻译： 本发明的掩模ROM响应于外部施加的命令在位线预充电操作之前选择性地放电位线。 列解码器响应于列选择信号选择位线之一。 放电控制电路根据该命令产生第一放电控制信号。 放电预解码器通过逻辑地组合第一放电控制信号和列选择信号来产生多个第二放电控制信号。 位线放电电路响应于第二放电控制信号选择性地放电位线。 由于特定存储器单元的选择，单元选择序列和所选单元的编程状态，掩模ROM没有位线耦合，导致读取速度的提高。

    Redundancy circuit and method of a semiconductor memory device
    9.
    发明授权
    Redundancy circuit and method of a semiconductor memory device 失效
    冗余电路和半导体存储器件的方法

    公开(公告)号：US5995422A

    公开(公告)日：1999-11-30

    申请号：US544439

    申请日：1995-11-17

    申请人： Heung-Soo Im ,  Sang-Ki Hwang ,  Hyong-Gon Lee

    发明人： Heung-Soo Im ,  Sang-Ki Hwang ,  Hyong-Gon Lee

    IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C7/00

    CPC分类号： G11C29/84

    摘要： The present invention provides a redundancy circuit in a semiconductor memory device which has spare memory cells which can store information that can be substituted for data of defective memory cells after the completion of the manufacturing process. If addresses designating the defective memory cells are externally input, the redundancy circuit generates a defective cell relief address signal which corresponds to the address designating the defective memory cell and is used to prevent defective data stored in normal memory cells from being output and causes correction data, to be substituted for the defective data output in correspondence with the defective cell relief address.

    摘要翻译： 本发明提供一种半导体存储器件中的冗余电路，该冗余电路具有备用存储器单元，其可以存储在制造过程完成之后可以代替有缺陷的存储器单元的数据的信息。 如果指定缺陷存储单元的地址是外部输入的，则冗余电路产生与指定有缺陷存储单元的地址对应的有缺陷的单元释放地址信号，并且用于防止存储在正常存储单元中的故障数据被输出并导致校正数据 ，以代替与有缺陷的单元缓冲地址对应的缺陷数据输出。