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公开(公告)号:US12190079B2
公开(公告)日:2025-01-07
申请号:US17716239
申请日:2022-04-08
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Munehiro Kozuma , Takeshi Aoki , Seiichi Yoneda , Yoshiyuki Kurokawa
Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.
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公开(公告)号:US12040007B2
公开(公告)日:2024-07-16
申请号:US17604523
申请日:2020-04-13
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Munehiro Kozuma , Takayuki Ikeda , Kei Takahashi , Takeshi Aoki
IPC: G11C11/4074 , G06F3/06 , G11C11/405 , G11C11/4096 , H01L27/12 , H01L29/786 , H10B12/00
CPC classification number: G11C11/4074 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G11C11/405 , G11C11/4096 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L29/78648 , H01L29/7869 , H10B12/00
Abstract: A semiconductor device with reduced power consumption is provided. The semiconductor device includes a transmitter unit, a receiver unit, a bias-outputting unit, and a controller unit. The bias-outputting unit has a plurality of memory units. The plurality of memory units each retains information to determine transmission power. The receiver unit receives a request signal transmitted from a base station and supplies it to the controller unit. The controller unit selects one of the plurality of memory units according to the request signal. The memory unit has an OS transistor and retains information when power supply is stopped.
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公开(公告)号:US11875837B2
公开(公告)日:2024-01-16
申请号:US17617969
申请日:2020-06-08
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Yoshiyuki Kurokawa , Munehiro Kozuma , Takeshi Aoki
IPC: G11C11/405 , G01N33/00 , G01V3/02 , H01L27/12 , H01L29/786 , H10B12/00
CPC classification number: G11C11/405 , G01N33/0001 , G01V3/02 , H01L27/124 , H01L27/1225 , H01L27/1255 , H01L29/7869 , H01L29/78648 , H10B12/00
Abstract: A semiconductor device resistant to a high temperature with low power consumption is provided. The semiconductor device includes a first and a second circuit, a first and a second cell, and a first and a second wiring. The first cell includes a first transistor, and the second cell includes a second transistor. The first and the second transistor operate in a subthreshold region. The first cell is electrically connected to the first circuit through the first wiring, the first cell is electrically connected to the second circuit through the second wiring, and the second cell is electrically connected to the second circuit through the second wiring. The first cell sets a current flowing through the first transistor to a first current and the second cell sets a current flowing through the second transistor to a second current. At this time, a potential corresponding to the second current is input from the second wiring to the first cell. Then, a third current flows from the second circuit to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the amount of the potential change and the first current.
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公开(公告)号:US11817780B2
公开(公告)日:2023-11-14
申请号:US17288957
申请日:2019-10-21
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Kei Takahashi , Takeshi Aoki
IPC: H02M3/155 , H02M1/00 , H01L27/12 , H01L29/786 , H10B12/00
CPC classification number: H02M3/155 , H01L27/124 , H01L27/1207 , H01L27/1225 , H01L27/1255 , H01L29/7869 , H01L29/78648 , H02M1/0009 , H10B12/00
Abstract: A power supply circuit with a novel structure is provided. The power supply circuit includes a power converter circuit supplying power to a load; a current sensing circuit generating a first signal including data on a current flowing through the load; a voltage sensing circuit generating a second signal including data on a voltage applied to the load; a correction circuit that includes a digital filter, a digital-analog converter circuit to which a signal output from the digital filter is input, and a sample-and-hold circuit for retaining a signal output from the digital-analog converter circuit and generates a third signal obtained by correcting the second signal; a selection circuit selecting the first signal or the third signal; an output circuit generating an output signal for controlling the power converter circuit in accordance with the signal selected by the selection circuit; and a control signal generation circuit controlling switching between a first operation for generating the output signal in accordance with the first signal and generating the third signal and a second operation for generating the output signal in accordance with the third signal.
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公开(公告)号:US11430820B2
公开(公告)日:2022-08-30
申请号:US17223248
申请日:2021-04-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Takeshi Aoki , Yoshiyuki Kurokawa , Takayuki Ikeda , Hikaru Tamura
IPC: H01L27/146 , G09G3/36 , H01L29/786
Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
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公开(公告)号:US11239268B2
公开(公告)日:2022-02-01
申请号:US16902124
申请日:2020-06-15
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Takeshi Aoki , Yoshiyuki Kurokawa , Takayuki Ikeda , Hikaru Tamura
IPC: H01L27/146 , G09G3/36 , H01L29/786
Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
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公开(公告)号:US10685992B2
公开(公告)日:2020-06-16
申请号:US16161209
申请日:2018-10-16
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Takeshi Aoki , Yoshiyuki Kurokawa , Takayuki Ikeda , Hikaru Tamura
IPC: H01L27/146 , G09G3/36 , H01L29/786
Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
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公开(公告)号:US09992442B2
公开(公告)日:2018-06-05
申请号:US15729169
申请日:2017-10-10
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Takeshi Aoki , Munehiro Kozuma , Yoshiyuki Kurokawa
CPC classification number: H04N5/455 , G11C14/0072 , H03M99/00 , H04H40/00 , H04N21/442
Abstract: A decoder with reduced power consumption is provided. The decoder includes a first circuit and a second circuit for holding data. The second circuit includes a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor include an oxide semiconductor in a channel formation region. The third transistor includes silicon in a channel formation region. A gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and a gate of the third transistor is electrically connected to one of a source and a drain of the second transistor. The decoder is configured to provide or stop power supply to the semiconductor device depending on a packet ID of a header portion of the data and to perform data storing or restoring of data between the first circuit and the second circuit.
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公开(公告)号:US09876499B2
公开(公告)日:2018-01-23
申请号:US15279594
申请日:2016-09-29
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Munehiro Kozuma , Takayuki Ikeda , Yoshiyuki Kurokawa , Takeshi Aoki , Yuki Okamoto
IPC: H03K19/177 , H03K19/00 , H03K19/0948
CPC classification number: H03K19/0013 , H03K19/0948 , H03K19/17728 , H03K19/1776
Abstract: A semiconductor device suitable for low-voltage driving. The semiconductor device includes a first transistor, a second transistor, a power supply line, a circuit, and a memory circuit. The first transistor controls electrical continuity between the circuit and the power supply line. The memory circuit stores data for setting a gate potential of the first transistor. The second transistor controls electrical continuity between an output node of the memory circuit and a gate of the first transistor. The second transistor is a transistor with an ultralow off-state current, for example, an oxide semiconductor transistor. In a period for operating the circuit, a first potential is input to the power supply line and the second transistor is turned off. In a period for updating the gate potential of the first transistor, a second potential is input to the power supply line. The second potential is higher than the first potential.
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公开(公告)号:US09761281B2
公开(公告)日:2017-09-12
申请号:US14602950
申请日:2015-01-22
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Takashi Nakagawa , Takayuki Ikeda , Yoshiyuki Kurokawa , Munehiro Kozuma , Takeshi Aoki
CPC classification number: G11C5/148 , G11C11/24 , G11C14/0054
Abstract: To provide a semiconductor device having a novel configuration, in which a malfunction and power consumption are reduced. A data holding circuit which includes a flipflop including first and second latch circuits and a shadow register including a nonvolatile memory portion; and a control signal generation circuit which generates a first control signal supplied to the first latch circuit and a second control signal supplied to the second latch circuit are included. The shadow register is a circuit which controls data saving or data restoring between the first and second latch circuits on the basis of a saving control signal or a restore control signal. The control signal generation circuit is a circuit which generates the first and second control signals at L level in a period during which data is saved or restored, on the basis of a clock signal, the saving control signal, and the restore control signal.
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