公开(公告)号：US06806184B2

公开(公告)日：2004-10-19

申请号：US10290630

申请日：2002-11-08

申请人： Ying-Ho Chen ,  Syun-Ming Jang

发明人： Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76838 ,  H01L21/7684

摘要： A new method is provided for the creation of copper interconnects. An opening is created in a layer of dielectric, a layer of barrier material is deposited. The layer of barrier material extends over the surface of the layer of dielectric. A film of copper is deposited over the surface of the layer of barrier material. The copper film is polished down to the surface of the layer of barrier material, creating a first copper interconnect. The created first copper interconnect is subjected to a thermal anneal, inducing copper hillocks in the surface of the first copper interconnect by releasing copper film stress in the first copper interconnect. The copper hillocks are then removed by polishing the surface of the created first copper interconnect down to the surface of the surrounding layer of dielectric, creating a second and final copper interconnect.

摘要翻译： 提供了一种用于创建铜互连的新方法。 在电介质层中产生开口，沉积一层屏障材料。 阻挡材料层在电介质层的表面上延伸。 一层铜沉积在阻挡材料层的表面上。 铜膜被抛光到阻挡材料层的表面，形成第一铜互连。 所制造的第一铜互连件经受热退火，通过在第一铜互连中释放铜膜应力，在第一铜互连表面上引起铜小丘。 然后通过将所形成的第一铜互连的表面抛光到电介质周围的表面，去除铜小丘，产生第二和最后的铜互连。

公开(公告)号：US06518183B1

公开(公告)日：2003-02-11

申请号：US09947782

申请日：2001-09-06

申请人： Weng Chang ,  Tien-I Bao ,  Ying-Ho Chen ,  Syun-Ming Jang

发明人： Weng Chang ,  Tien-I Bao ,  Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： H01L2144

CPC分类号： H01L21/76883 ,  H01L21/76834

摘要： Within a method for fabricating a microelectronic fabrication having formed therein a copper containing conductor layer passivated with a passivation layer, there is first: (1) pre-heated the copper containing conductor layer to a temperature of from about 300 to about 450 degrees centigrade for a time period of from about 30 to about 120 seconds to form a pre-heated copper containing conductor layer; and then (2) plasma treated the pre-heated copper containing conductor layer within a reducing plasma to form a plasma treated pre-heated copper containing conductor layer; prior to (3)forming upon the plasma treated pre-heated copper containing conductor layer the passivation layer. The foregoing process sequence provides for attenuated hillock defects within the plasma treated pre-heated copper containing conductor layer when forming the passivation layer thereupon.

摘要翻译： 在其中形成有钝化层钝化的含铜导体层的微电子制造方法中，首先：（1）将含铜导体层预热至约300至约450摄氏度的温度，用于 约30至约120秒的时间段以形成预热的含铜导体层; 然后（2）在还原等离子体中等离子体处理预热的含铜导体层，以形成等离子体处理的预热含铜导体层; 在（3）在等离子体处理的预热含铜导体层上形成钝化层之前。 当在其上形成钝化层时，上述工艺顺序提供等离子体处理的预热含铜导体层内的衰减的小丘缺陷。

公开(公告)号：US06194307B1

公开(公告)日：2001-02-27

申请号：US09298930

申请日：1999-04-26

申请人： Ying-Ho Chen ,  Syun-Ming Jang

发明人： Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/7684

摘要： After the first layer of copper has been deposited and polished (to form the pattern of copper damascene conducting lines) a layer of Ta or TaN/Cu is deposited. Another thin layer of copper is deposited thereby filling existing pores and recesses in the polished copper lines. A second CMP is applied to the surface of the second deposited layer of copper, this second CMP removes the redundant copper from the space where the Inter Metal Dielectric (IMD) layer will be created. Prior to the deposition of the second layer of copper, a (brief) etchback of the (surface of the) first layer of copper can be performed in order to enhance copper surface integrity and thereby improve the deposition of the second layer of copper. A layer of TaN/Ta and a layer of seed copper can be deposited within the openings for the damascene conducting lines prior to the deposition of these lines.

摘要翻译： 在第一层铜被沉积和抛光之后（形成铜镶嵌导电线的图案），沉积一层Ta或TaN / Cu。 沉积另一薄铜层，从而填充抛光铜线中的现有孔和凹槽。 第二CMP施加到第二沉积铜层的表面上，该第二CMP从产生金属间介质（IMD）层的空间中去除冗余铜。 在沉积第二层铜之前，可以执行铜（第一层）的（表面）的（简短的）回蚀，以便增强铜表面的完整性，从而改善第二层铜的沉积。 在沉积这些线之前，可以在用于镶嵌导电线的开口内沉积一层TaN / Ta和一层种子铜。

公开(公告)号：US6143673A

公开(公告)日：2000-11-07

申请号：US409888

申请日：1999-10-01

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Shwangming Jeng ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Shwangming Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/311 ,  H01L21/316 ,  H01L21/31

CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/31116 ,  H01L21/31612

摘要： A method for forming within a microelectronics fabrication a dielectric layer formed over, around and between patterned conductor layers. There is first provided a substrate employed within a microelectronics fabrication upon which is formed a patterned conductor layers. There is then formed over the patterned conductor layer a silicon oxide dielectric layer. There is then treated the silicon oxide dielectric layer to an anisotropic sputter etching process to remove silicon oxide dielectric material without re-deposition from the bottom of the gap between lines of the patterned conductor layer and to reform the silicon oxide dielectric layers on the sidewalls of the patterned lines to form spacer layers thereon. Both the silicon oxide dielectric layer deposition process and the sputter etching process may be repeated as desired to form the desired depth of trench and shape of spacer layer. There is then exposed the substrate to a nitrogen plasma. There is then formed over the substrate a gap filling silicon oxide dielectric layer to complete the formation of the inter-level dielectric layer with minimal void content in gaps between patterned lines.

摘要翻译： 在微电子制造中形成在图案化导体层之上，周围和之间形成介电层的方法。 首先提供在微电子制造中使用的衬底，其上形成图案化的导体层。 然后在图案化的导体层上形成氧化硅介电层。 然后将氧化硅介电层处理成各向异性溅射蚀刻工艺以去除氧化硅介电材料，而不从图案化导体层的线之间的间隙的底部重新沉积，并且重新形成在图案化导体层的侧壁上的氧化硅介电层 图案化线以在其上形成间隔层。 可以根据需要重复氧化硅介电层沉积工艺和溅射蚀刻工艺，以形成期望的沟槽深度和间隔层的形状。 然后将基板暴露于氮等离子体。 然后在衬底上形成填充氧化硅介电层的间隙，以在图案化线之间的间隙中以最小的空隙含量完成层间电介质层的形成。

公开(公告)号：US06049137A

公开(公告)日：2000-04-11

申请号：US106331

申请日：1998-06-29

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chung-Long Chang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chung-Long Chang ,  Chen-Hua Yu

IPC分类号： H01L23/544 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S148/102 ,  Y10S438/975

摘要： A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48. Etches are used to remove the residual insulating layer 46A, silicon nitride layer 44, and pad oxide layer 42 in the alignment mark area 30 thereby exposing the alignment marks 48 and making the alignment marks readable.

摘要翻译： 可读取的对准标记的结构和在半导体衬底上的对准标记区域中制造可读取的对准标记的方法。 提供了包括产品区域12和对准标记区域30的半导体衬底10。 对准标记区域30具有外部区域40和内部区域50.外部区域40围绕内部区域50.多个对准标记沟槽24形成在内部区域50内的衬底10中。衬垫氧化物层20 并且在至少对准标记区域12中顺序地形成氮化硅层44.隔离沟槽43至少在外部区域40中形成在基板10中。绝缘层46至少形成在对准标记区域30的上方 绝缘层46进行化学机械抛光，从而从内部对准标记区域50除去绝缘层的第一厚度，并且在对准标记沟槽48中留下残留绝缘层46A。使用蚀刻来去除残留绝缘层46A ，氮化硅层44和衬垫氧化物层42，从而露出对准标记48并使对准标记可读。

公开(公告)号：US6043136A

公开(公告)日：2000-03-28

申请号：US121710

申请日：1998-07-24

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： A method for forming a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a silicon oxide layer, where the silicon oxide layer is formed through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material at an ozone:TEOS volume ratio of from about 10:1 to about 14:1. Finally, there is then annealed thermally the substrate within an oxygen containing atmosphere at a temperature of greater than about 1100 degrees centigrade to form from the silicon oxide layer a densified silicon oxide layer. The densified silicon oxide layer formed employing the method is formed with an unexpectedly low shrinkage.

摘要翻译： 一种形成氧化硅层的方法。 首先提供基板。 然后在衬底上形成氧化硅层，其中通过使用臭氧氧化剂和四乙基原硅酸盐（TEOS）的臭氧辅助亚大气压力热化学气相沉积（SACVD）方法形成氧化硅层 ）硅源材料：TEOS体积比为约10:1至约14:1。 最后，在含氧气氛中，在大于约1100摄氏度的温度下将衬底热处理，从氧化硅层形成致密氧化硅层。 使用该方法形成的致密氧化硅层形成意想不到的低收缩率。

公开(公告)号：US6043133A

公开(公告)日：2000-03-28

申请号：US121708

申请日：1998-07-24

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Jui-Yu Chang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Jui-Yu Chang ,  Chen-Hua Yu

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： The present invention provides a method of removing an shallow trench isolation (STI) oxide layer 38 from over alignment marks 30. The invention has two major features: (1) A STI photoresist mask 42A that is used to etch Alignment area trenches 34 around alignment marks 30 and to etch STI trenches 35 in device areas 14; and (2) A "reverse tone" STI photoresist mask 42B that is used to remove the isolation oxide 38 from over the alignment marks 30 and from over the active areas 37. The method begins by providing a substrate 10 having a device area 14, an alignment mark trench area 16; and an alignment mark area 18. A polish stop layer 20 22 is formed over the substrate 10. A trench isolation resist layer 42A is used to etch alignment area trenches 34 around the alignment marks 34 and STI trenches 35 in the device areas. A dielectric layer 38 is formed over the substrate. In a key step, the reverse tone trench isolation resist layer 42B is used to etch the first dielectric layer 38 from over the alignment marks 30 and the Active areas 27. Next, the remaining first dielectric layer 38 is chemical-mechanical polished thereby planarizing the first dielectric layer 38.

摘要翻译： 本发明提供从超过对准标记30去除浅沟槽隔离（STI）氧化物层38的方法。本发明具有两个主要特征：（1）STI光刻胶掩模42A，用于蚀刻对准区域沟槽34周围的对准 标记30并蚀刻设备区域14中的STI沟槽35; 和（2）用于从对准标记30上方和从有源区域37上方去除隔离氧化物38的“反向色调”STI光刻胶掩模42B。该方法开始于提供具有器件区域14的衬底10， 对准标记沟槽区域16; 和对准标记区域18.在衬底10上形成抛光阻挡层20 22.沟槽隔离抗蚀剂层42A用于蚀刻围绕器件区域中的对准标记34和STI沟槽35的对准区域沟槽34。 介电层38形成在衬底上。 在关键步骤中，反向色调沟槽隔离抗蚀剂层42B用于从对准标记30和有源区27上方蚀刻第一介电层38.接下来，剩余的第一介电层38进行化学机械抛光，从而平面化 第一电介质层38。

公开(公告)号：US5817566A

公开(公告)日：1998-10-06

申请号：US810389

申请日：1997-03-03

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method for filling a trench within a substrate. There is first providing a substrate having a trench formed within the substrate. There is then formed over the substrate and within the trench a gap filling silicon oxide trench fill layer. The gap filling silicon oxide trench fill layer is formed through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method. The method employs an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material at an ozone: TEOS volume ratio of less than about 2:1. Finally, the substrate is annealed thermally within an oxygen containing atmosphere at a temperature of greater than about 1100 degrees centigrade to form from the gap filling silicon oxide trench fill layer a densified gap filling silicon oxide trench fill layer. Through the method there is formed a densified gap filling silicon oxide trench fill layer with a limited surface sensitivity, a low etch rate and a limited shrinkage. Through an analogous method employing an ozone oxidant and a tetra-ethyl-orth-silicate (TEOS) silicon source material at an ozone: TEOS volume ratio of from about 10:1 to about 14:1 there may be formed a densified gap filling silicon oxide layer with exceedingly low shrinkage.

摘要翻译： 一种填充衬底内的沟槽的方法。 首先提供在衬底内形成沟槽的衬底。 然后在衬底上并在沟槽内形成填充氧化硅沟槽填充层的间隙。 通过臭氧辅助亚大气压热化学气相沉积（SACVD）方法形成填充氧化硅沟槽填充层的间隙。 该方法采用臭氧氧化剂和四乙基原硅酸盐（TEOS）硅源材料，其臭氧：TEOS体积比小于约2:1。 最后，将衬底在含氧气氛中在大于约1100摄氏度的温度下进行热退火，从填充氧化硅沟槽填充层的间隙形成填充氧化硅沟槽填充层的致密间隙。 通过该方法，形成了具有有限表面灵敏度，低蚀刻速率和有限收缩的密集填充氧化硅沟槽填充层的间隙填充层。 通过使用臭氧氧化剂和硅酸四乙基硅酸盐（TEOS）硅源材料的臭氧：TEOS体积比为约10:1至约14:1的类似方法，可以形成致密化的间隙填充硅 氧化层具有极低的收缩率。

公开(公告)号：US5786260A

公开(公告)日：1998-07-28

申请号：US767015

申请日：1996-12-16

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chung-Long Chang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chung-Long Chang ,  Chen-Hua Yu

IPC分类号： H01L23/544 ,  H01L23/58

CPC分类号： H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S148/102 ,  Y10S438/975

摘要： A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48. Etches are used to remove the residual insulating layer 46A, silicon nitride layer 44, and pad oxide layer 42 in the alignment mark area 30 thereby exposing the alignment marks 48 and making the alignment marks readable.

摘要翻译： 可读取的对准标记的结构和在半导体衬底上的对准标记区域中制造可读取的对准标记的方法。 提供了包括产品区域12和对准标记区域30的半导体衬底10。 对准标记区域30具有外部区域40和内部区域50.外部区域40围绕内部区域50.多个对准标记沟槽24形成在内部区域50内的衬底10中。衬垫氧化物层20 并且在至少对准标记区域12中顺序地形成氮化硅层44.隔离沟槽43至少在外部区域40中形成在基板10中。绝缘层46至少形成在对准标记区域30的上方 绝缘层46进行化学机械抛光，从而从内部对准标记区域50除去绝缘层的第一厚度，并且在对准标记沟槽48中留下残留绝缘层46A。使用蚀刻来去除残留绝缘层46A ，氮化硅层44和衬垫氧化物层42，从而露出对准标记48并使对准标记可读。

公开(公告)号：US5726090A

公开(公告)日：1998-03-10

申请号：US850135

申请日：1997-05-01

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： An improved method of gap filling shallow trench isolation with ozone-TEOS is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate. A thermal oxide layer is grown within the isolation trenches. A plasma enhanced SiH.sub.4 oxide layer is deposited over the nitride layer and over the thermal oxide layer within the isolation trenches and treated with N.sub.2 plasma. Thereafter, an ozone-TEOS layer is deposited overlying the plasma enhanced SiH.sub.4 oxide layer and filling the isolation trenches. The ozone-TEOS layer and the plasma enhanced SiH.sub.4 oxide layer are polished away stopping at the nitride layer. This completes the formation of shallow trench isolation in the fabrication of the integrated circuit device.

摘要翻译： 描述了利用臭氧-TEOS进行间隙填充浅沟槽隔离的改进方法。 衬垫氧化物层设置在半导体衬底的表面上。 在衬垫氧化物层上沉积氮化物层。 通过氮化物层和衬垫氧化物层将多个隔离沟槽蚀刻到半导体衬底中。 在隔离沟槽内生长热氧化物层。 等离子体增强的SiH 4氧化物层沉积在氮化物层上方并在隔离沟槽内的热氧化物层上方并且用N 2等离子体处理。 此后，沉积臭氧TEOS层，覆盖等离子体增强的SiH 4氧化物层并填充隔离沟槽。 在氮化物层处停止臭氧TEOS层和等离子体增强SiH 4氧化物层。 这完成了在集成电路器件的制造中浅沟槽隔离的形成。