公开(公告)号：US20110156667A1

公开(公告)日：2011-06-30

申请号：US12726340

申请日：2010-03-17

Applicant: Jui-Yu Chang ,  Chih-Wei Chen ,  Jin-Lien Lin

Inventor： Jui-Yu Chang ,  Chih-Wei Chen ,  Jin-Lien Lin

IPC: G05F1/00

CPC classification number: G05F1/563 ,  G05F1/575

Abstract: A voltage regulator includes an amplifier, a power device, a delay signal generator, and a voltage-generating circuit. The amplifier generates a control signal according to a reference voltage and a feedback voltage. The power switch generates the output voltage by regulating the output current according to the switch control signal. The delay signal generator generates a plurality of sequential delay signals each having distinct delay time with respect to an externally applied power-on burst signal. The voltage-generating circuit provides an equivalent resistance for generating the feedback voltage corresponding to the output voltage, and regulates the output voltage by adjusting the equivalent resistance according to the plurality of sequential delay signals.

Abstract translation: 电压调节器包括放大器，功率器件，延迟信号发生器和产生电压的电路。 放大器根据参考电压和反馈电压产生控制信号。 电源开关通过根据开关控制信号调节输出电流来产生输出电压。 延迟信号发生器产生多个相对于外部施加的上电突发信号具有不同延迟时间的顺序延迟信号。 电压产生电路提供用于产生对应于输出电压的反馈电压的等效电阻，并且通过根据多个顺序延迟信号调整等效电阻来调节输出电压。

公开(公告)号：US20080180162A1

公开(公告)日：2008-07-31

申请号：US11668473

申请日：2007-01-30

Applicant: Jui-Yu Chang

Inventor： Jui-Yu Chang

IPC: G05F1/10

CPC classification number: H03L7/0896

Abstract: A charge pump includes a first switch coupled between a first voltage source and a first node, second switch coupled between the first node and a second node, a third switch coupled between the second node and a third node, the third node is for outputting from the charge pump. A fourth switch is coupled between the output node and a fourth node, a fifth switch is coupled between the fourth node and a fifth node, and a sixth switch is coupled between the fifth node and ground. A seventh switch is coupled between ground and the first node and an eighth switch is coupled between a second voltage source and the fifth node. A first capacitor is coupled between the second node and a first voltage signal and a second capacitor is coupled between the fourth node and a second voltage signal.

Abstract translation: 电荷泵包括耦合在第一电压源和第一节点之间的第一开关，耦合在第一节点和第二节点之间的第二开关，耦合在第二节点和第三节点之间的第三开关，第三节点用于从 电荷泵。 第四开关耦合在输出节点和第四节点之间，第五开关耦合在第四节点和第五节点之间，第六开关耦合在第五节点和地之间。 第七开关耦合在地和第一节点之间，第八开关耦合在第二电压源和第五节点之间。 第一电容器耦合在第二节点和第一电压信号之间，第二电容器耦合在第四节点和第二电压信号之间。

公开(公告)号：US6043133A

公开(公告)日：2000-03-28

申请号：US121708

申请日：1998-07-24

Applicant: Syun-Ming Jang ,  Ying-Ho Chen ,  Jui-Yu Chang ,  Chen-Hua Yu

Inventor： Syun-Ming Jang ,  Ying-Ho Chen ,  Jui-Yu Chang ,  Chen-Hua Yu

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: The present invention provides a method of removing an shallow trench isolation (STI) oxide layer 38 from over alignment marks 30. The invention has two major features: (1) A STI photoresist mask 42A that is used to etch Alignment area trenches 34 around alignment marks 30 and to etch STI trenches 35 in device areas 14; and (2) A "reverse tone" STI photoresist mask 42B that is used to remove the isolation oxide 38 from over the alignment marks 30 and from over the active areas 37. The method begins by providing a substrate 10 having a device area 14, an alignment mark trench area 16; and an alignment mark area 18. A polish stop layer 20 22 is formed over the substrate 10. A trench isolation resist layer 42A is used to etch alignment area trenches 34 around the alignment marks 34 and STI trenches 35 in the device areas. A dielectric layer 38 is formed over the substrate. In a key step, the reverse tone trench isolation resist layer 42B is used to etch the first dielectric layer 38 from over the alignment marks 30 and the Active areas 27. Next, the remaining first dielectric layer 38 is chemical-mechanical polished thereby planarizing the first dielectric layer 38.

Abstract translation: 本发明提供从超过对准标记30去除浅沟槽隔离（STI）氧化物层38的方法。本发明具有两个主要特征：（1）STI光刻胶掩模42A，用于蚀刻对准区域沟槽34周围的对准 标记30并蚀刻设备区域14中的STI沟槽35; 和（2）用于从对准标记30上方和从有源区域37上方去除隔离氧化物38的“反向色调”STI光刻胶掩模42B。该方法开始于提供具有器件区域14的衬底10， 对准标记沟槽区域16; 和对准标记区域18.在衬底10上形成抛光阻挡层20 22.沟槽隔离抗蚀剂层42A用于蚀刻围绕器件区域中的对准标记34和STI沟槽35的对准区域沟槽34。 介电层38形成在衬底上。 在关键步骤中，反向色调沟槽隔离抗蚀剂层42B用于从对准标记30和有源区27上方蚀刻第一介电层38.接下来，剩余的第一介电层38进行化学机械抛光，从而平面化 第一电介质层38。

公开(公告)号：US5933744A

公开(公告)日：1999-08-03

申请号：US54302

申请日：1998-04-02

Applicant: Jeng-Horng Chen ,  Tsu Shih ,  Jui-Yu Chang ,  Chung-Long Chang

Inventor： Jeng-Horng Chen ,  Tsu Shih ,  Jui-Yu Chang ,  Chung-Long Chang

IPC: H01L21/3105 ,  H01L23/544 ,  H01L21/465 ,  H01L21/76

CPC classification number: H01L23/544 ,  H01L21/31053 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

Abstract: A method of alignment for a chemical mechanical polishing includes previously patterning a primary zero alignment mark on a surface of a wafer. A first dielectric layer is deposited on the wafer for isolation. Then, an etching is used to etch the first dielectric layer using a photoresist as a mask. First conductive plugs are formed in the first dielectric layer. Next, a first conductive layer is formed on the surface of the first dielectric layer and on the tungsten plugs. Thus, the first non-zero alignment mark pattern is formed on the surface of the first conductive layer and aligned to the first conductive plugs. Next, a second non-zero alignment mark pattern is thus formed on the surface of a second conductive layer and aligned to the a second conductive plugs. By repeating the aforementioned method, odd non-zero alignment mark patterns will be formed over the first non-zero alignment mark pattern, and even non-zero alignment mark patterns will be formed over the second non-zero alignment mark pattern. Therefore, the present invention save space to put non-zero alignment marks in multilevel interconnection and planarization processes.

Abstract translation: 用于化学机械抛光的对准方法包括预先对晶片表面上的初级零对准标记进行图案化。 第一介电层沉积在晶片上用于隔离。 然后，使用蚀刻来使用光致抗蚀剂作为掩模蚀刻第一介电层。 在第一电介质层中形成第一导电插塞。 接下来，在第一电介质层的表面和钨插塞上形成第一导电层。 因此，第一非零对准标记图案形成在第一导电层的表面上并与第一导电插塞对准。 接下来，在第二导电层的表面上形成第二非零对准标记图案，并与第二导电插塞对准。 通过重复上述方法，将在第一非零对准标记图案上形成奇数非零对准标记图案，并且甚至在第二非零对准标记图案上形成非零对准标记图案。 因此，本发明节省空间，将非零对准标记放置在多层互连和平面化处理中。

公开(公告)号：US5923996A

公开(公告)日：1999-07-13

申请号：US867312

申请日：1997-06-02

Applicant: Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

Inventor： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC: H01L23/544 ,  H01L21/46 ,  H01L21/301 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L2223/5442 ,  H01L2223/54493 ,  H01L2924/0002

Abstract: A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical polishing (CMP) process. Complete protection is provided by recessing the alignment mark into the substrate by etching. Recess etching is accomplished at the same time the isolation trenches are followed to delineate device areas. Thus, alignment marks are provided with a protective recess without extra steps. Furthermore, by forming alignment marks at the outer perimeter of the wafer, productivity is improved by providing maximum usage of wafer area for integrated circuits.

Abstract translation: 公开了一种用于在晶片的外周边形成对准标记的方法，其中它们在化学机械抛光（CMP）工艺期间不会受到很大的损害。 通过蚀刻将对准标记凹入衬底来提供完整的保护。 在同时完成凹槽蚀刻，同时遵循隔离沟以描绘器件区域。 因此，对准标记设置有保护凹槽而没有额外的步骤。 此外，通过在晶片的外周形成对准标记，通过提供用于集成电路的晶片面积的最大使用来提高生产率。

公开(公告)号：US20130070876A1

公开(公告)日：2013-03-21

申请号：US13421872

申请日：2012-03-16

Applicant: Hsin-Ta Wu ,  Jui-Yu Chang ,  Jau-Jr Lin

Inventor： Hsin-Ta Wu ,  Jui-Yu Chang ,  Jau-Jr Lin

IPC: H04B1/16

CPC classification number: H03D7/14 ,  H04B1/06 ,  H04B1/16 ,  H04B7/0452 ,  H04H40/90 ,  H04L27/00

Abstract: A low-noise block downconverter (LNB) is disclosed. The low-noise block downconverter comprises a first input module, for outputting a first intermediate frequency (IF) signal after receiving a first polarization signal via a first input end; a second input module, for outputting a second IF signal after receiving a second polarization signal via a second input end; a first output module, coupled to the first input module, for amplifying the first IF signal, to output a first user signal to a first user; and a second output module, coupled to the second input module, for amplifying the second IF signal, to output a second user signal to a second user.

Abstract translation: 公开了一种低噪声块下变频器（LNB）。 低噪声块下变频器包括第一输入模块，用于经由第一输入端接收第一极化信号后输出第一中频（IF）信号; 第二输入模块，用于在经由第二输入端接收到第二偏振信号之后输出第二IF信号; 第一输出模块，耦合到第一输入模块，用于放大第一IF信号，以将第一用户信号输出到第一用户; 以及第二输出模块，耦合到第二输入模块，用于放大第二IF信号，以将第二用户信号输出到第二用户。

公开(公告)号：US08289008B2

公开(公告)日：2012-10-16

申请号：US12726340

申请日：2010-03-17

Applicant: Jui-Yu Chang ,  Chih-Wei Chen ,  Jin-Lien Lin

Inventor： Jui-Yu Chang ,  Chih-Wei Chen ,  Jin-Lien Lin

IPC: G05F1/40

CPC classification number: G05F1/563 ,  G05F1/575

Abstract: A voltage regulator includes an amplifier, a power device, a delay signal generator, and a voltage-generating circuit. The amplifier generates a control signal according to a reference voltage and a feedback voltage. The power switch generates the output voltage by regulating the output current according to the switch control signal. The delay signal generator generates a plurality of sequential delay signals each having distinct delay time with respect to an externally applied power-on burst signal. The voltage-generating circuit provides an equivalent resistance for generating the feedback voltage corresponding to the output voltage, and regulates the output voltage by adjusting the equivalent resistance according to the plurality of sequential delay signals.

Abstract translation: 电压调节器包括放大器，功率器件，延迟信号发生器和产生电压的电路。 放大器根据参考电压和反馈电压产生控制信号。 电源开关通过根据开关控制信号调节输出电流来产生输出电压。 延迟信号发生器产生多个相对于外部施加的上电突发信号具有不同延迟时间的顺序延迟信号。 电压产生电路提供用于产生对应于输出电压的反馈电压的等效电阻，并且通过根据多个顺序延迟信号调整等效电阻来调节输出电压。

公开(公告)号：US06444371B1

公开(公告)日：2002-09-03

申请号：US09377541

申请日：1999-08-19

Applicant: Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

Inventor： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC: G03F900

CPC classification number: H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

Abstract: Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

Abstract translation: 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US6020249A

公开(公告)日：2000-02-01

申请号：US891088

申请日：1997-07-10

Applicant: Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

Inventor： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC: G03F9/00 ,  H01L23/544 ,  H01L23/48

CPC classification number: G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002

Abstract: A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

公开(公告)号：US5858588A

公开(公告)日：1999-01-12

申请号：US850133

申请日：1997-05-01

Applicant: Jui-Yu Chang ,  Chunshing Chen ,  Syun-Ming Jang ,  Ying-Ho Chen

Inventor： Jui-Yu Chang ,  Chunshing Chen ,  Syun-Ming Jang ,  Ying-Ho Chen

IPC: H01L23/544 ,  G03F9/00

CPC classification number: H01L23/544 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002

Abstract: A mask pattern and method are described for the recovery of alignment marks on an integrated circuit wafer without the use of additional masks. The mask pattern and method provide means to recover the alignment marks after forming a metal layer on a planarized inter-level dielectric layer. The pattern which conventional methods have placed on a separate mask is formed in the end regions of a mask used for forming a pattern on the active region of the wafer. In order to fit the pattern in the end regions of the mask the pattern is divided into two parts. When the pattern is used to expose a layer of photoresist two exposure steps are used.

Abstract translation: 描述了用于在集成电路晶片上恢复对准标记的掩模图案和方法，而不使用附加掩模。 掩模图案和方法提供了在平坦化的层间电介质层上形成金属层之后恢复对准标记的装置。 在用于在晶片的有源区上形成图案的掩模的端部区域中形成常规方法已经放置在单独的掩模上的图案。 为了将图案装配在掩模的端部区域中，图案被分为两部分。 当使用图案曝光一层光致抗蚀剂时，使用两个曝光步骤。