公开(公告)号：US06795168B2

公开(公告)日：2004-09-21

申请号：US10117838

申请日：2002-04-08

申请人： Yao-Ting Wang ,  Christophe Pierrat ,  Fang-Cheng Chang

发明人： Yao-Ting Wang ,  Christophe Pierrat ,  Fang-Cheng Chang

IPC分类号： G03B2754

CPC分类号： G03F7/70208 ,  G03F7/70283

摘要： One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.

摘要翻译： 本发明的一个实施例提供一种在集成电路制造过程中有助于使晶片通过至少两个掩模的系统。 该系统包括辐射源和两个或更多个照明器。 这些照明器中的每一个接收来自辐射源的辐射，并且使用辐射来照射标线架座。 然后通过每个光罩保持器的辐射在光合成器中通过成像光学器件，成像光学器件将组合的辐射投影到半导体晶片上。

公开(公告)号：US06787271B2

公开(公告)日：2004-09-07

申请号：US10085759

申请日：2002-02-28

申请人： Michel Luc Côté ,  Christophe Pierrat

发明人： Michel Luc Côté ,  Christophe Pierrat

IPC分类号： G03F900

CPC分类号： G03F7/70466 ,  G03F1/26 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/70558

摘要： A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

公开(公告)号：US06753115B2

公开(公告)日：2004-06-22

申请号：US10029041

申请日：2001-12-20

申请人： Youping Zhang ,  Christophe Pierrat

发明人： Youping Zhang ,  Christophe Pierrat

IPC分类号： G03F900

CPC分类号： G03F1/36

摘要： One embodiment of the invention provides a system that facilitates minimum spacing and/or width control during an optical proximity correction operation for a layout of a mask used in manufacturing an integrated circuit. During operation, the system considers a target edge of a first feature on the mask and then identifies a set of interacting edges in proximity to the target edge. Next, the system performs the optical proximity correction operation, wherein performing the optical proximity correction operation involves applying a first edge bias to the target edge to compensate for optical effects in a resulting image of the target edge. While applying the first edge bias to the target edge, the system allocates an available bias between the first edge bias for the target edge and a second edge bias for at least one edge in the set of interacting edges.

摘要翻译： 本发明的一个实施例提供一种在用于制造集成电路的掩模的布局的光学邻近校正操作期间促进最小间隔和/或宽度控制的系统。 在操作期间，系统考虑掩模上的第一特征的目标边缘，然后识别在目标边缘附近的一组交互边缘。 接下来，系统执行光学邻近校正操作，其中执行光学邻近校正操作包括将第一边缘偏压施加到目标边缘以补偿目标边缘的所得图像中的光学效果。 在将第一边缘偏压施加到目标边缘的同时，系统为目标边缘的第一边缘偏置和相互作用边缘集合中的至少一个边缘的第二边缘偏置分配可用偏置。

公开(公告)号：US06665856B1

公开(公告)日：2003-12-16

申请号：US09728885

申请日：2000-12-01

申请人： Christophe Pierrat ,  Youping Zhang

发明人： Christophe Pierrat ,  Youping Zhang

IPC分类号： G06F1750

CPC分类号： G03F1/36 ,  G03F1/68 ,  G03F7/70441

摘要： Techniques for forming a fabrication layout, such as a mask, for a physical design layout, such as a layout for an integrated circuit, include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.

摘要翻译： 用于形成用于物理设计布局（例如集成电路的布局）的诸如掩模的制造布局的技术包括使用邻近效应模型来校正邻近效应的制造布局。 执行邻近效应模型以产生初始输出。 初始输出基于制造布局中的段的第一位置。 第一位置从原始制造布局中的相应原始边缘移位等于初始偏置的距离。 还执行该模型以基于该段的第二位置产生第二输出。 第二位置从相应的原始边缘移位等于第二偏置的距离。 基于初始输出和第二输出确定段的最佳偏差。 基于最佳偏差，该段在制造布局中从相应的边缘移位。

公开(公告)号：US06635393B2

公开(公告)日：2003-10-21

申请号：US09816619

申请日：2001-03-23

申请人： Christophe Pierrat

发明人： Christophe Pierrat

IPC分类号： G03F900

CPC分类号： G03F1/30 ,  G03F1/50

摘要： A conductive blank enables election beam (e-beam) patterning rather than optical patterning for the phase level etch of a phase-shifting mask (PSM) photomask. The conductive blank includes a conductive layer between a chrome (pattern) layer and a quartz substrate. The chrome layer is patterned with in-phase and phased features, and then is recoated with a resist layer. An e-beam exposure tool exposes the resist layer over the phased features. The still intact conductive layer under the chrome layer dissipates any charge buildup in the resist layer during this process. A phase level etch then etches through the conductive layer and creates a pocket in the quartz. A subsequent isotropic etch through both the in-phase and phased features removes the conductive layer at the in-phase features and improves exposure radiation transmission intensity. Alternatively, a visually transparent conductive layer can be used, eliminating the need to etch through the in-phase features.

公开(公告)号：US06584609B1

公开(公告)日：2003-06-24

申请号：US09514551

申请日：2000-02-28

申请人： Christophe Pierrat ,  You-Ping Zhang ,  Fang-Cheng Chang ,  Hoyong Park ,  Yao-Ting Wang

发明人： Christophe Pierrat ,  You-Ping Zhang ,  Fang-Cheng Chang ,  Hoyong Park ,  Yao-Ting Wang

IPC分类号： G06F1750

CPC分类号： G03F1/70 ,  G03F1/36 ,  G06F17/5068

摘要： A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.

摘要翻译： 公开了一种半导体布局测试和校正系统。 该系统结合基于规则的光学邻近校正和基于模型的光学邻近校正，以便测试和校正半导体布局。 在第一实施例中，半导体布局首先由基于规则的光学邻近校正系统处理，然后由基于模型的光学邻近校正系统进行处理。 在另一个实施例中，系统首先使用基于规则的光学邻近校正系统处理半导体布局，然后使用基于模型的光学邻近校正系统来选择性地处理困难的特征。 在另一个实施例中，系统使用基于规则的光学邻近校正系统或基于模型的光学邻近校正系统选择性地处理半导体布局的各种特征。

公开(公告)号：US06558854B2

公开(公告)日：2003-05-06

申请号：US09732816

申请日：2000-12-08

申请人： Christophe Pierrat ,  J. Brett Rolfson

发明人： Christophe Pierrat ,  J. Brett Rolfson

IPC分类号： G03F900

CPC分类号： G03F1/30 ,  G03F1/26

摘要： A phase shifting mask can be used to form features on a semiconductor wafer with exposure lights of two different wavelengths. The depth of the phase shifting layer is calculated and fabricated such that it shifts a first exposure light about 180° and a second exposure light about 180°.

摘要翻译： 可以使用相移掩模在具有两种不同波长的曝光灯的半导体晶片上形成特征。 计算并制造相移层的深度，使得其移动约180°的第一曝光光和约180°的第二曝光光。

公开(公告)号：US06541165B1

公开(公告)日：2003-04-01

申请号：US09669367

申请日：2000-09-26

申请人： Christophe Pierrat

发明人： Christophe Pierrat

IPC分类号： G03F900

CPC分类号： G03F1/30 ,  G03F1/36

摘要： Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. Both opaque field phase shift masks and complementary binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer are produced.

摘要翻译： 提供了技术，用于将相移技术的使用扩展到在集成电路层中复杂布局的掩模的实现，超出了过去已经限制了这种结构的所选临界尺寸特征，例如晶体管栅极。 该方法包括识别可以对其进行相移的特征，自动映射用于实现这些特征的相移区域，解决根据给定设计规则可能发生的相位冲突，以及在相移区域内应用子分辨率辅助特征 和光学邻近校正特征到相移区域。 产生不完整的场相移掩模和定义互连结构的互补二进制掩模和不使用相移定义的其它类型的结构，这些结构对于完成层的布局是必需的。

公开(公告)号：US06432619B1

公开(公告)日：2002-08-13

申请号：US09943995

申请日：2001-08-30

申请人： Nanseng Jeng ,  Christophe Pierrat

发明人： Nanseng Jeng ,  Christophe Pierrat

IPC分类号： G03F720

摘要： A method for forming a photomask including applying photoresist to a semiconductor substrate, exposing a first area of the photoresist to a first dosage of radiation, and exposing a second area of the photoresist to a second dosage of radiation. The first and second areas may be concurrently exposed. First and second regions of the photoresist are then removed to form first and second openings that have different depths in the photoresist. Such removal may be effected by developing the first and second areas of the photoresist. One of the openings may extend down to an insulating layer formed on the semiconductor substrate. A contact and/or trench etch may be performed to remove. a portion of the insulating layer. Conductive material may then be deposited in the opening so formed to form a contact, a via, or another electrically conductive element that communicates with a structure underlying the insulating layer.

公开(公告)号：US06379847B2

公开(公告)日：2002-04-30

申请号：US09426386

申请日：1999-10-25

申请人： Douglas J. Cutter ,  Christophe Pierrat

发明人： Douglas J. Cutter ,  Christophe Pierrat

IPC分类号： G03F900

CPC分类号： G03F1/34 ,  G03F1/26 ,  G03F1/30 ,  G03F1/32 ,  G03F7/70291

摘要： An electronically programmed mask is connected to an electronic device, such as a processor. In operation, a mask design is first entered into the processor. The processor controls a display of an image on the electronically programmed mask, wherein the display replicates conventional type masks. The electronically programmed mask is designed such that the display presented on its screen provides optical contrast and characteristics that are easily changed or reprogrammed by the processor. Electronically controlled masks provide the same patterns as mechanical type masks without requiring rigid, permanent type structures to form a desired pattern.