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1.发明授权Method and apparatus for analyzing a layout using an instance-based representation 有权用于使用基于实例的表示来分析布局的方法和装置公开(公告)号：US06560766B2
公开(公告)日：2003-05-06
申请号：US09917526
申请日：2001-07-26
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
摘要翻译： 本发明的一个实施例提供一种系统，其使用包括布局的一组几何特征的基于实例的表示来分析与半导体芯片上的电路相关的布局。 系统通过接收布局的表示来操作，其中所述表示定义包括一个或多个几何特征的多个节点。 接下来，系统通过识别布局中相同的节点实例的多次发生，将表示转换为基于实例的表示，其中可以进一步处理每个节点实例而不必考虑外部因素对节点实例的影响。 然后，系统通过仅处理每个节点实例一次对基于实例的表示进行进一步的处理，由此在布局中的多个节点实例的出现上不必重复该处理。
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公开(公告)号：US06988259B2
公开(公告)日：2006-01-17
申请号：US10327454
申请日：2002-12-20
CPC分类号： G03F1/70 , G03F1/36 , G06F17/5068
摘要： A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.
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公开(公告)号：US06721928B2
公开(公告)日：2004-04-13
申请号：US10323565
申请日：2002-12-17
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.
摘要翻译： 本发明使用基于实例的（IB）表示来减少验证从参考布局生成的经转换的布局所需的时间。 具体来说，从参考布局生成基于IB的表示。 基于IB的表示包括包括主实例单元和从实例单元的实例单元的集合。 需要模拟每组实例单元的一个子集，以验证转换后的布局。
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4.发明授权Method and apparatus for exposing a wafer using multiple masks during an integrated circuit manufacturing process 有权在集成电路制造过程中使用多个掩模曝光晶片的方法和装置公开(公告)号：US06795168B2
公开(公告)日：2004-09-21
申请号：US10117838
申请日：2002-04-08
IPC分类号： G03B2754
CPC分类号： G03F7/70208 , G03F7/70283
摘要： One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.
摘要翻译： 本发明的一个实施例提供一种在集成电路制造过程中有助于使晶片通过至少两个掩模的系统。 该系统包括辐射源和两个或更多个照明器。 这些照明器中的每一个接收来自辐射源的辐射，并且使用辐射来照射标线架座。 然后通过每个光罩保持器的辐射在光合成器中通过成像光学器件，成像光学器件将组合的辐射投影到半导体晶片上。
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公开(公告)号：US06584609B1
公开(公告)日：2003-06-24
申请号：US09514551
申请日：2000-02-28
IPC分类号： G06F1750
CPC分类号： G03F1/70 , G03F1/36 , G06F17/5068
摘要： A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.
摘要翻译： 公开了一种半导体布局测试和校正系统。 该系统结合基于规则的光学邻近校正和基于模型的光学邻近校正，以便测试和校正半导体布局。 在第一实施例中，半导体布局首先由基于规则的光学邻近校正系统处理，然后由基于模型的光学邻近校正系统进行处理。 在另一个实施例中，系统首先使用基于规则的光学邻近校正系统处理半导体布局，然后使用基于模型的光学邻近校正系统来选择性地处理困难的特征。 在另一个实施例中，系统使用基于规则的光学邻近校正系统或基于模型的光学邻近校正系统选择性地处理半导体布局的各种特征。
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6.发明授权Method and apparatus for data hierarchy maintenance in a system for mask description 有权用于掩模描述的系统中的数据层级维护的方法和装置公开(公告)号：US06453452B1
公开(公告)日：2002-09-17
申请号：US09154397
申请日：1998-09-16
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated. As the first program data is maintained in a true hierarchical format, layouts which are operated upon in accordance with this method are able to be processed through conventional design rule checkers. Further, this method is capable of being applied to all types of layouts including light and dark field designs and phase shifting layouts.
摘要翻译： 一种用于对分级描述的集成电路布局执行操作的方法和装置，从而提供维护布局的原始层级。 该方法包括提供分层描述的布局作为第一输入，并提供与作为第二输入执行的操作相对应的特定操作标准集合。 然后可以根据特定的操作标准集在布局上执行掩模操作，其可以包括诸如OPC和诸如NOT和OR的逻辑操作的操作。 然后响应于布局操作产生包括对应于分层描述的布局的分层配置的校正数据的第一程序数据，使得如果第一程序数据被应用于平坦化布局，则输出包括表示执行操作的结果的数据 将生成布局。 由于第一程序数据以真正的分层格式维护，所以根据该方法操作的布局能够通过常规的设计规则检查器进行处理。 此外，该方法能够应用于所有类型的布局，包括浅色和暗场设计以及相移布局。
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公开(公告)号：US06370679B1
公开(公告)日：2002-04-09
申请号：US09154415
申请日：1998-09-16
IPC分类号： G06F760
CPC分类号： G03F1/36
摘要： A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input, and a particular set of OPC correction criteria as a second input. The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria. After the areas on the mask which need correction have been identified, optical proximity correction data is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout. As the output correction data is maintained in true hierarchical format, layouts which are OPC corrected according to this method are able to be processed through conventional design rule checkers with no altering of the data.
摘要翻译： 提供了用于校正维持原始布局的原始真实层级的光学邻近效应的集成电路布局的方法和装置。 还提供了用于对光学邻近效应进行了校正的布局的设计规则检查的方法和装置。 OPC校正方法包括提供分级描述的集成电路布局作为第一输入和作为第二输入的特定的OPC校正标准集合。 然后分析集成电路布局以识别满足所提供的OPC校正标准的布局的特征。 在已经识别出需要校正的掩模上的区域之后，响应于特定的校正标准集而产生光学邻近校正数据。 最后，生成将生成的光学邻近校正数据存储在与集成电路布局的层次结构对应的层次结构中的第一程序数据。 由于输出校正数据以真实的分层格式保持，所以根据该方法校正OPC的布局能够通过传统的设计规则检查器进行处理，而不改变数据。
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公开(公告)号：US07360191B2
公开(公告)日：2008-04-15
申请号：US10984210
申请日：2004-11-08
申请人： Li-Fu Chang , Yao-Ting Wang , Fang-Cheng Chang
发明人： Li-Fu Chang , Yao-Ting Wang , Fang-Cheng Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5036
摘要： Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.
摘要翻译： 提供了集成电路（“IC”）制造中定时驱动形状闭合的系统和方法。 这些集成设计制造过程（“IDMP”）包括将IC制造定时和几何验证过程的信息集成到IC设计中的增量流。 增量流是增量流，其包括用于处理与电路表征参数相关联的差异信息的δ-几何时序预测过程和/或Δ-时间形状预测过程。 delta流程使用与电路特性参数对应的差异或增量信息独立地重新表征IC设计。 增量流提供增量或重新表征器件和互连结构的相应参数的增量输出（增量），而不需要生成新的电路特征参数，而无需重新处理IC设计的所有信息。
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9.发明授权Method and apparatus for data hierarchy maintenance in a system for mask description 有权用于掩模描述的系统中的数据层级维护的方法和装置公开(公告)号：US07356788B2
公开(公告)日：2008-04-08
申请号：US10173198
申请日：2002-06-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated. As the first program data is maintained in a true hierarchical format, layouts which are operated upon in accordance with this method are able to be processed through conventional design rule checkers. Further, this method is capable of being applied to all types of layouts including light and dark field designs and phase shifting layouts.
摘要翻译： 一种用于对分级描述的集成电路布局执行操作的方法和装置，从而提供维护布局的原始层级。 该方法包括提供分层描述的布局作为第一输入，并提供与作为第二输入执行的操作相对应的特定操作标准集合。 然后可以根据特定的操作标准集在布局上执行掩模操作，其可以包括诸如OPC和诸如NOT和OR的逻辑操作的操作。 然后响应于布局操作产生包括对应于分层描述的布局的分层配置的校正数据的第一程序数据，使得如果第一程序数据被应用于平坦化布局，则输出包括表示执行操作的结果的数据 将生成布局。 由于第一程序数据以真正的分层格式维护，所以根据该方法操作的布局能够通过常规的设计规则检查器进行处理。 此外，该方法能够应用于所有类型的布局，包括浅色和暗场设计以及相移布局。
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公开(公告)号：US20050172251A1
公开(公告)日：2005-08-04
申请号：US10984443
申请日：2004-11-08
申请人： Li-Fu Chang , Yao-Ting Wang , Fang-Cheng Chang
发明人： Li-Fu Chang , Yao-Ting Wang , Fang-Cheng Chang
IPC分类号： G06F17/50 , H01L20060101
CPC分类号： G06F17/5031 , G06F17/5036
摘要： Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.
摘要翻译： 提供了集成电路（“IC”）制造中定时驱动形状闭合的系统和方法。 这些集成设计制造过程（“IDMP”）包括将IC制造定时和几何验证过程的信息集成到IC设计中的增量流。 增量流是增量流，其包括用于处理与电路表征参数相关联的差异信息的δ-几何时序预测过程和/或Δ-时间形状预测过程。 delta流程使用与电路特性参数对应的差异或增量信息独立地重新表征IC设计。 增量流提供增量或重新表征器件和互连结构的相应参数的增量输出（增量），而不需要生成新的电路特征参数，而无需重新处理IC设计的所有信息。
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