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公开(公告)号：US06988259B2
公开(公告)日：2006-01-17
申请号：US10327454
申请日：2002-12-20
CPC分类号： G03F1/70 , G03F1/36 , G06F17/5068
摘要： A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.
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公开(公告)号：US06584609B1
公开(公告)日：2003-06-24
申请号：US09514551
申请日：2000-02-28
IPC分类号： G06F1750
CPC分类号： G03F1/70 , G03F1/36 , G06F17/5068
摘要： A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.
摘要翻译： 公开了一种半导体布局测试和校正系统。 该系统结合基于规则的光学邻近校正和基于模型的光学邻近校正，以便测试和校正半导体布局。 在第一实施例中，半导体布局首先由基于规则的光学邻近校正系统处理，然后由基于模型的光学邻近校正系统进行处理。 在另一个实施例中，系统首先使用基于规则的光学邻近校正系统处理半导体布局，然后使用基于模型的光学邻近校正系统来选择性地处理困难的特征。 在另一个实施例中，系统使用基于规则的光学邻近校正系统或基于模型的光学邻近校正系统选择性地处理半导体布局的各种特征。
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公开(公告)号：US06721928B2
公开(公告)日：2004-04-13
申请号：US10323565
申请日：2002-12-17
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.
摘要翻译： 本发明使用基于实例的（IB）表示来减少验证从参考布局生成的经转换的布局所需的时间。 具体来说，从参考布局生成基于IB的表示。 基于IB的表示包括包括主实例单元和从实例单元的实例单元的集合。 需要模拟每组实例单元的一个子集，以验证转换后的布局。
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4.发明授权Method and apparatus for analyzing a layout using an instance-based representation 有权用于使用基于实例的表示来分析布局的方法和装置公开(公告)号：US06560766B2
公开(公告)日：2003-05-06
申请号：US09917526
申请日：2001-07-26
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
摘要翻译： 本发明的一个实施例提供一种系统，其使用包括布局的一组几何特征的基于实例的表示来分析与半导体芯片上的电路相关的布局。 系统通过接收布局的表示来操作，其中所述表示定义包括一个或多个几何特征的多个节点。 接下来，系统通过识别布局中相同的节点实例的多次发生，将表示转换为基于实例的表示，其中可以进一步处理每个节点实例而不必考虑外部因素对节点实例的影响。 然后，系统通过仅处理每个节点实例一次对基于实例的表示进行进一步的处理，由此在布局中的多个节点实例的出现上不必重复该处理。
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5.发明授权Method and apparatus for exposing a wafer using multiple masks during an integrated circuit manufacturing process 有权在集成电路制造过程中使用多个掩模曝光晶片的方法和装置公开(公告)号：US06795168B2
公开(公告)日：2004-09-21
申请号：US10117838
申请日：2002-04-08
IPC分类号： G03B2754
CPC分类号： G03F7/70208 , G03F7/70283
摘要： One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.
摘要翻译： 本发明的一个实施例提供一种在集成电路制造过程中有助于使晶片通过至少两个掩模的系统。 该系统包括辐射源和两个或更多个照明器。 这些照明器中的每一个接收来自辐射源的辐射，并且使用辐射来照射标线架座。 然后通过每个光罩保持器的辐射在光合成器中通过成像光学器件，成像光学器件将组合的辐射投影到半导体晶片上。
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公开(公告)号：US07523027B2
公开(公告)日：2009-04-21
申请号：US10878847
申请日：2004-06-28
IPC分类号： G06F17/50
CPC分类号： G06T7/0004 , G03F1/26 , G03F1/36 , G03F1/84 , G03F7/70441 , G03F7/705 , G06F17/5068 , G06T2207/30148
摘要： A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask. The method may also include providing a second simulated image which is a simulation of the wafer print of the portion of the design mask which corresponds to the portion represented by the defect area image. The method also provides for the comparison of the first and second simulated images in order to determine the printability of any identified potential defects on the photolithography mask. A method of determining the process window effect of any identified potential defects is also provided for.
摘要翻译： 提供了一种用于检查用于缺陷的光刻掩模的方法和装置。 检查方法包括向图像模拟器提供缺陷区域图像，其中缺陷区域图像是光刻掩模的一部分的图像，并且提供一组光刻参数作为图像模拟器的第二输入。 缺陷区域图像可以由检查工具提供，该检查工具使用高分辨率显微镜扫描光刻掩模以获得缺陷，并捕获围绕所识别的潜在缺陷的掩模区域的图像。 图像模拟器响应于缺陷区域图像和光刻参数集合而生成第一模拟图像。 第一模拟图像是如果将晶片暴露于通过该掩模的该部分的照明源而将被印刷在晶片上的图像的模拟。 该方法还可以包括提供第二模拟图像，其是对应于由缺陷区域图像表示的部分的设计掩模的部分的晶片印刷的模拟。 该方法还提供了第一和第二模拟图像的比较，以便确定光刻掩模上任何识别的潜在缺陷的可印刷性。 还提供了确定任何识别的潜在缺陷的过程窗口效应的方法。
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公开(公告)号：US07107571B2
公开(公告)日：2006-09-12
申请号：US09906920
申请日：2001-07-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/26 , G03F1/36 , G03F1/84 , G03F7/70441 , G03F7/705 , G06T7/0004 , G06T2207/30148
摘要： A system and method of analyzing defects on a mask used in lithography are provided. A defect area image is provided as a first input, a set of lithography parameters is provided as a second input, and a set of metrology data is provided as a third input. The defect area image comprises an image of a portion of the mask. A simulated image can be generated in response to the first input. The simulated image comprises a simulation of an image that would be printed on a wafer if the wafer were exposed to a radiation source directed at the portion of the mask. The characteristics of the radiation source comprise the set of lithography parameters and the characteristics of the mask comprise the set of metrology data.
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8.发明授权Conflict sensitive compaction for resolving phase-shift conflicts in layouts for phase-shifted features 有权用于解决相移特征的布局中的相移冲突的冲突敏感压缩公开(公告)号：US06622288B1
公开(公告)日：2003-09-16
申请号：US09823146
申请日：2001-03-29
IPC分类号： G06F1750
CPC分类号： G03F1/30
摘要： Techniques for forming a design layout with phase-shifted features, such as an integrated circuit layout, include receiving information about a particular phase-shift conflict in a first physical design layout. The information indicates one or more features logically associated with the particular phase-shift conflict. Then the first physical design layout is adjusted based on that information to produce a second design layout. The adjustments rearrange features in a unit of the design layout to collect free space around a selected feature associated with the phase-shift conflict. With these techniques, a unit needing more space for additional shifters can obtain the needed space during the physical design process making the adjustment. The needed space so obtained allows the fabrication design process to avoid or resolve phase conflicts while forming a fabrication layout, such as a mask, for substantiating the design layout in a printed features layer, such as in an actual integrated circuit.
摘要翻译： 用于形成具有诸如集成电路布局的相移特征的设计布局的技术包括在第一物理设计布局中接收关于特定相移冲突的信息。 该信息指示与特定相移冲突逻辑关联的一个或多个特征。 然后根据该信息调整第一个物理设计布局以产生第二个设计布局。 调整重新排列设计布局中的功能，以收集与相移冲突相关的所选功能周围的可用空间。 利用这些技术，在进行调整的物理设计过程中，需要更多空间的单元可以获得额外的移位器的空间。 如此获得的所需空间允许制造设计过程避免或解决相位冲突，同时形成诸如掩模的制造布局，用于证实印刷特征层（例如在实际集成电路中）的设计布局。
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公开(公告)号：US07216320B2
公开(公告)日：2007-05-08
申请号：US10984443
申请日：2004-11-08
申请人： Li-Fu Chang , Yao-Ting Wang , Fang-Cheng Chang
发明人： Li-Fu Chang , Yao-Ting Wang , Fang-Cheng Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.
摘要翻译： 提供了集成电路（“IC”）制造中定时驱动形状闭合的系统和方法。 这些集成设计制造过程（“IDMP”）包括将IC制造定时和几何验证过程的信息集成到IC设计中的增量流。 增量流是增量流，其包括用于处理与电路表征参数相关联的差异信息的δ-几何时序预测过程和/或Δ-时间形状预测过程。 delta流程使用与电路特性参数对应的差异或增量信息独立地重新表征IC设计。 增量流提供增量或重新表征器件和互连结构的相应参数的增量输出（增量），而不需要生成新的电路特征参数，而无需重新处理IC设计的所有信息。
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公开(公告)号：US20060242618A1
公开(公告)日：2006-10-26
申请号：US11354398
申请日：2006-02-14
申请人： Yao-Ting Wang , Chi-Ming Tsai , Fang-Cheng Chang
发明人： Yao-Ting Wang , Chi-Ming Tsai , Fang-Cheng Chang
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/705 , G06F17/5081
摘要： Systems and methods are provided for programming and running simulation engines of lithographic simulations on GPUs. This integration of lithographic simulations includes the hosting on one or more GPUs of any of a variety of lithographic techniques, including for example resolution enhancement technologies, optical proximity correction, optical rule-checking or lithography checking, and model-based DRC, where operations of one or more techniques are run in parallel. The systems and methods provided also include the integration of lithographic geometry operations into GPUs to obtain improved performance. Examples of this integration include a Design Rule Checker (DRC), parasitic extraction, and placement and route for example.
摘要翻译： 提供了用于编程和运行GPU上光刻仿真的仿真引擎的系统和方法。 光刻模拟的这种集成包括在一个或多个GPU上托管各种光刻技术中的任何一种，包括例如分辨率增强技术，光学邻近校正，光学规则检查或光刻检查以及基于模型的DRC，其中操作 一个或多个技术并行运行。 所提供的系统和方法还包括将平版印刷几何操作集成到GPU中以获得改进的性能。 这种集成的示例包括设计规则检查器（DRC），寄生提取，以及放置和路由。
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