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公开(公告)号：US20080189486A1
公开(公告)日：2008-08-07
申请号：US11928113
申请日：2007-10-30
申请人： David Nguyen , Nan Nan , Jim Chin-Nan Ni , Charles C. Lee , Ming-Shiang Shen
发明人： David Nguyen , Nan Nan , Jim Chin-Nan Ni , Charles C. Lee , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/1416 , G06F21/32 , G06F21/78 , G06K19/07 , G06K19/07354 , G06K19/07732 , G06K19/07743 , G07C9/00087
摘要： USB flash memory devices with an improved cap are described. According to an exemplary embodiment of the invention, a USB flash memory device comprises a flash memory drive, an improved cap, a cap plug and a wire loop. The flash memory drive comprises a core unit and an outer shell structure. The cap comprises a substantially slab-shaped hollow structure with rounded edges and rounded corners, having an open end and a closed end, two opposing side walls, a top surface and a bottom surface. The cap is configured to substantially encase the entire flash memory drive through the open end, when the flash memory drive is in a closed configuration. The cap plug is configured to plug into the cap, when the flash memory drive is in an open configuration. The wire loop is configured to link the flash memory drive and the cap plug together in one location.
摘要翻译： 描述了具有改进的盖的USB闪存设备。 根据本发明的示例性实施例，USB闪存设备包括闪存驱动器，改进的盖，盖塞和线环。 闪存驱动器包括核心单元和外壳结构。 盖包括具有圆形边缘和圆角的基本上平板状的中空结构，其具有开口端和封闭端，两个相对的侧壁，顶表面和底表面。 当闪存驱动器处于关闭配置时，盖被配置为基本上将整个闪存驱动器封装在开放端。 当闪存驱动器处于打开配置时，盖插头被配置为插入盖子。 线环配置为在一个位置将闪存驱动器和盖塞连接在一起。
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52.发明授权Memory address management systems in a large capacity multi-level cell (MLC) based flash memory device 有权大容量多级单元（MLC）闪存设备中的内存地址管理系统公开(公告)号：US08015348B2
公开(公告)日：2011-09-06
申请号：US12980591
申请日：2010-12-29
IPC分类号： G06F12/08
CPC分类号： H05K1/182 , G06F12/00 , H01R13/447 , H05K1/181 , H05K5/0278 , H05K2201/10189 , H05K2201/10446 , H05K2203/1572
摘要： Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.
摘要翻译： 描述了在大容量多级基于单元的闪存设备中管理存储器地址的方法和系统。 根据一个方面，一种闪存设备包括一个使用索引方案来管理逻辑到物理地址相关的处理单元。 闪存被分为N组。 每个集合包括多个条目（即，块）。 对于物理块号和相关联的页面使用信息（以下称为“PLTPPUI”）的N组部分逻辑条目号被存储在基于MLC的闪速存储器的保留区域中。 只有一个N集被加载以寻址相关和页面使用存储器（ACPUM），这是一个有限大小的随机存取存储器（RAM）。 在一个实施例中，静态RAM（SRAM）被实现用于地址相关的快速访问时间。 与数据传输请求一起接收的LSA指示将N组PLTPPUI中的哪一个加载到ACPUM中。
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公开(公告)号：US07676640B2
公开(公告)日：2010-03-09
申请号：US11864652
申请日：2007-09-28
IPC分类号： G06F13/10
CPC分类号： G06F8/654
摘要： An electronic data flash card is accessible by a host system, and includes a flash memory controller and at least one flash memory device coupled to the flash controller. The boot code and control code for the flash memory system (flash card) are stored in the flash memory device during a programming procedure. The flash controller transfers the boot code and control code to a volatile main memory (e.g., random access memory or RAM) at start up or reset making a RAM-based memory system. Boot code and control code are selectively overwritten during a code updating operation. A single flash controller thus supports multiple brands and types of flash memory to eliminate stocking issues.
摘要翻译： 电子数据闪存卡可由主机系统访问，并且包括闪存控制器和耦合到闪存控制器的至少一个闪存设备。 闪存系统（闪存卡）的启动代码和控制代码在编程过程中存储在闪存设备中。 闪存控制器在启动或复位时将引导代码和控制代码传送到易失性主存储器（例如，随机存取存储器或RAM），从而形成基于RAM的存储器系统。 引导代码和控制代码在代码更新操作期间被有选择地覆盖。 因此，单个闪存控制器支持多种品牌和类型的闪存，以消除存货问题。
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54.发明申请公开(公告)号：US20080320209A1
公开(公告)日：2008-12-25
申请号：US12141879
申请日：2008-06-18
CPC分类号： G06F13/161 , G06F12/0246 , G06F2212/7201 , G06F2212/7203
摘要： High performance and endurance non-volatile memory (NVM) based storage systems are disclosed. According to one aspect of the present invention, a NVM based storage system comprises at least one intelligent NVM device. Each intelligent NVM device includes a control interface logic and NVM. Logical-to-physical address conversion is performed within the control interface logic, thereby eliminating the need of address conversion in a storage system level controller. In another aspect, a volatile memory buffer together with corresponding volatile memory controller and phase-locked loop circuit is included in a NVM based storage system. The volatile memory buffer is partitioned to two parts: a command queue; and one or more page buffers. The command queue is configured to hold received data transfer commands by the storage protocol interface bridge, while the page buffers are configured to hold data to be transmitted between the host computer and the at least one NVM device.
摘要翻译： 公开了基于高性能和耐久性非易失性存储器（NVM）的存储系统。 根据本发明的一个方面，一种基于NVM的存储系统包括至少一个智能NVM设备。 每个智能NVM设备都包括一个控制接口逻辑和NVM。 在控制接口逻辑中执行逻辑到物理地址转换，从而消除了存储系统级控制器中地址转换的需要。 在另一方面，在基于NVM的存储系统中包括易失性存储器缓冲器以及相应的易失性存储器控制器和锁相环电路。 易失性存储缓冲区分为两部分：命令队列; 和一个或多个页面缓冲区。 命令队列被配置为通过存储协议接口桥保存接收到的数据传输命令，而页缓冲器被配置为保存要在主计算机和至少一个NVM设备之间传输的数据。
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55.发明申请Non-Volatile Memory Device Manufacturing Process Testing Systems and Methods Thereof 失效非易失性存储器件制造工艺测试系统及其方法公开(公告)号：US20080201622A1
公开(公告)日：2008-08-21
申请号：US12042316
申请日：2008-03-04
CPC分类号： G11C29/56 , G11C5/04 , G11C16/04 , G11C2029/0409
摘要： Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.
摘要翻译： 描述了制造和测试非易失性存储器（NVM）器件的系统和方法。 根据一个示例性实施例，在制造NVM模块期间的功能测试是通过包括计算机和经由外部总线耦合到计算机的NVM测试仪的系统进行的。 NVM测试仪包括多个槽。 每个插槽被配置为容纳待测试的相应的一个NVM模块。 NVM测试器被配置为包括输入/输出接口，具有相关联的RAM和ROM的微控制器，数据发生器，地址发生器，比较器，比较状态存储空间，测试结果指示器和NVM模块检测器。 数据发生器产生可重复的数据位序列作为测试向量。 已知的测试向量写入被测NVM模块的NVM。 然后将已知的测试向量与从NVM模块检索的数据进行比较。
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公开(公告)号：US20080147968A1
公开(公告)日：2008-06-19
申请号：US12017249
申请日：2008-01-21
IPC分类号： G06F12/02
CPC分类号： G06F11/1068 , G11C5/04
摘要： High performance flash memory devices (FMD) are described. According to one exemplary embodiment of the invention, a high performance FMD includes an I/O interface, a FMD controller, and at least one non-volatile memory module along with corresponding at least one channel controller. The I/O interface is configured to connect the high performance FMD to a host computing device The FMD contoller is configured to control data transfer (e.g., data reading, data writing/programming, and data erasing) operations between the host computing device and the non-volatile memory module. The at least one non-volatile memory module, comprising one or more non-volatile memory chips, is configured as a secondary storage for the host computing device. The at least one channel controller is configured to ensure proper and efficient data transfer between a set of data buffers located in the FMD controller and the at least one non-volatile memory module.
摘要翻译： 描述了高性能闪存设备（FMD）。 根据本发明的一个示例性实施例，高性能FMD包括I / O接口，FMD控制器以及至少一个非易失性存储器模块以及对应的至少一个通道控制器。 I / O接口被配置为将高性能FMD连接到主机计算设备FMD控制器被配置为控制主计算设备和主计算设备之间的数据传输（例如，数据读取，数据写入/编程和数据擦除）操作 非易失性内存模块。 包括一个或多个非易失性存储器芯片的至少一个非易失性存储器模块被配置为主计算设备的辅助存储器。 至少一个通道控制器被配置为确保位于FMD控制器和至少一个非易失性存储器模块中的一组数据缓冲器之间的适当和有效的数据传输。
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公开(公告)号：US08078794B2
公开(公告)日：2011-12-13
申请号：US11926743
申请日：2007-10-29
IPC分类号： G06F13/00
CPC分类号： G06F12/1416 , G06F3/0613 , G06F3/0643 , G06F3/0688 , G06F12/0246 , G06F12/0866 , G06F21/32 , G06F21/78 , G06F2212/2022 , G06F2212/7202 , G07C9/00087 , G11C2211/5641
摘要： Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array.
摘要翻译： 描述了使用单级单元（SLC）和多级单元（MLC）闪存阵列的组合的混合固态驱动器（SSD）。 根据本发明的一个方面，使用组合SLC和MLC闪存阵列构建混合SSD。 SSD还包括一个微控制器，用于控制和协调从主机计算设备到MLC闪存阵列的SLC闪存阵列的数据传输。 存储器选择指示符通过基于一个或多个标准进行分类数据文件来确定，所述标准包括但不限于将系统文件和用户目录存储在SLC闪速存储器阵列中并将用户文件存储在MLC闪速存储器阵列中; 或将更频繁的访问文件存储在SLC闪存阵列中，而在MLC闪存阵列中访问的文件较少。
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公开(公告)号：US20110197017A1
公开(公告)日：2011-08-11
申请号：US13089898
申请日：2011-04-19
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/214 , G06F2212/7208 , G11C2211/5641
摘要： High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.
摘要翻译： 描述了高耐久性非易失性存储器件（NVMD）。 高耐久性NVMD包括I / O接口，NVM控制器，CPU以及易失性存储器子系统和至少一个非易失性存储器（NVM）模块。 易失性存储器缓存子系统被配置为数据高速缓存子系统。 当NVMD适用于主机系统时，至少一个NVM模块被配置为数据存储器。 I / O接口被配置为从主机接收数据缓存子系统的传入数据，并将请求数据从数据缓存子系统发送到主机。 至少一个NVM模块可以包括至少第一和第二类型的NVM。 第一种类型包括SLC闪存，而第二种类型的MLC闪存。 NVM的第一种类型被配置为数据高速缓存子系统和第二类NVM之间的缓冲区。
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公开(公告)号：US20110029723A1
公开(公告)日：2011-02-03
申请号：US12885451
申请日：2010-09-18
CPC分类号： G06K19/07743 , A45C2011/188 , G06K19/07732 , H05K1/117 , H05K1/118 , H05K1/189 , H05K3/284 , H05K3/4691 , H05K2201/091 , H05K2201/10159 , H05K2203/1527
摘要： Non-volatile memory based computer systems and methods are described. According to one aspect of the invention, at least one non-volatile memory module is coupled to a computer system as main storage. The non-volatile memory module is controlled by a northbridge controller configured to control the non-volatile memory as main memory. The page size of the at least one non-volatile memory module is configured to be the size of one of the cache lines associated with a microprocessor of the computer system. According to another aspect, at least one non-volatile memory module is coupled to a computer system as data read/write buffer of one or more hard disk drives. The non-volatile memory module is controlled by a southbridge controller configured to control the non-volatile memory as an input/out device. The page size of the at least one non-volatile memory module is configured in proportion to characteristics of the hard disk drives.
摘要翻译： 描述了基于非易失性存储器的计算机系统和方法。 根据本发明的一个方面，至少一个非易失性存储器模块耦合到作为主存储器的计算机系统。 非易失性存储器模块由配置成将非易失性存储器控制为主存储器的北桥控制器来控制。 至少一个非易失性存储器模块的页面大小被配置为与计算机系统的微处理器相关联的高速缓存行之一的大小。 根据另一方面，至少一个非易失性存储器模块作为一个或多个硬盘驱动器的数据读/写缓冲器耦合到计算机系统。 非易失性存储器模块由配置成将非易失性存储器控制为输入/输出设备的南桥控制器来控制。 至少一个非易失性存储器模块的页面大小被配置成与硬盘驱动器的特性成比例。
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公开(公告)号：US07865809B1
公开(公告)日：2011-01-04
申请号：US12166191
申请日：2008-07-01
IPC分类号： H03M13/00
CPC分类号： G06F11/1076 , G06F11/1068 , H03M13/153 , H03M13/1535 , H03M13/1545 , H03M13/6561
摘要： Data error detection and correction in non-volatile memory devices are disclosed. Data error detection and correction can be performed with software, hardware or a combination of both. Generally an error corrector is referred to as an ECC (error correction code). One of the most relevant codes using in non-volatile memory devices is based on BCH (Bose, Ray-Chaudhuri, Hocquenghem) code. In order to correct reasonable number (e.g., up to 8-bit (eight-bit)) of random errors in a chunk of data (e.g., a codeword of 4200-bit with 4096-bit information data), a BCH(4200,4096,8) is used in GF(213). ECC comprises encoder and decoder. The decoder further comprises a plurality of error detectors and one error corrector. The plurality of error decoders is configured for calculating odd terms of syndrome polynomial for multiple channels in parallel, while the error corrector is configured for sequentially calculating even terms of syndrome polynomial, key solver and error location.
摘要翻译： 公开了非易失性存储器件中的数据错误检测和校正。 可以通过软件，硬件或两者的组合来执行数据错误检测和校正。 通常，误差校正器被称为ECC（纠错码）。 在非易失性存储器件中使用的最相关的代码之一是基于BCH（Bose，Ray-Chaudhuri，Hocquenghem）代码。 为了纠正数据块（例如，具有4096位信息数据的4200位的码字）中的合理数量（例如，高达8位（8位））的随机错误，BCH（4200， 4096,8）用于GF（213）。 ECC包括编码器和解码器。 解码器还包括多个误差检测器和一个误差校正器。 所述多个误差解码器被配置为并行地计算多个通道的奇数项的奇数项，而所述误差校正器被配置为顺序地计算校正子多项式，密钥求解器和误差位置的偶数项。
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