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公开(公告)号：US07953931B2
公开(公告)日：2011-05-31
申请号：US12035398
申请日：2008-02-21
IPC分类号： G06F12/12
CPC分类号： G06F13/161 , G06F12/0246 , G06F12/0862 , G06F12/123 , G06F2212/7203 , G11C11/5621 , G11C11/5678 , G11C13/0004 , G11C2211/5641 , G11C2211/5643
摘要： High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.
摘要翻译： 描述了高耐久性非易失性存储器件（NVMD）。 高耐久性NVMD包括I / O接口，NVM控制器，CPU以及易失性存储器子系统和至少一个非易失性存储器（NVM）模块。 易失性存储器缓存子系统被配置为数据高速缓存子系统。 当NVMD适用于主机系统时，至少一个NVM模块被配置为数据存储器。 I / O接口被配置为从主机接收数据缓存子系统的传入数据，并将请求数据从数据缓存子系统发送到主机。 至少一个NVM模块可以包括至少第一和第二类型的NVM。 第一种类型包括SLC闪存，而第二种类型的MLC闪存。 NVM的第一种类型被配置为数据高速缓存子系统和第二类NVM之间的缓冲区。
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2.发明申请MEMORY ADDRESS MANAGEMENT SYSTEMS IN A LARGE CAPACITY MULTI-LEVEL CELL (MLC) BASED FLASH MEMORY DEVICE 有权基于大容量多级电池（MLC）的闪存存储器件中的存储器地址管理系统公开(公告)号：US20110093653A1
公开(公告)日：2011-04-21
申请号：US12980591
申请日：2010-12-29
IPC分类号： G06F12/00
CPC分类号： H05K1/182 , G06F12/00 , H01R13/447 , H05K1/181 , H05K5/0278 , H05K2201/10189 , H05K2201/10446 , H05K2203/1572
摘要： Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.
摘要翻译： 描述了在大容量多级基于单元的闪存设备中管理存储器地址的方法和系统。 根据一个方面，一种闪存设备包括一个使用索引方案来管理逻辑到物理地址相关的处理单元。 闪存被分为N组。 每个集合包括多个条目（即，块）。 对于物理块号和相关联的页面使用信息（以下称为“PLTPPUI”）的N组部分逻辑条目号被存储在基于MLC的闪速存储器的保留区域中。 只有一个N集被加载以寻址相关和页面使用存储器（ACPUM），这是一个有限大小的随机存取存储器（RAM）。 在一个实施例中，静态RAM（SRAM）被实现用于地址相关的快速访问时间。 与数据传输请求一起接收的LSA指示将N组PLTPPUI中的哪一个加载到ACPUM中。
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公开(公告)号：US07827348B2
公开(公告)日：2010-11-02
申请号：US12017249
申请日：2008-01-21
IPC分类号： G06F12/00
CPC分类号： G06F11/1068 , G11C5/04
摘要： High performance flash memory devices (FMD) are described. According to one exemplary embodiment of the invention, a high performance FMD includes an I/O interface, a FMD controller, and at least one non-volatile memory module along with corresponding at least one channel controller. The I/O interface is configured to connect the high performance FMD to a host computing device The FMD contoller is configured to control data transfer (e.g., data reading, data writing/programming, and data erasing) operations between the host computing device and the non-volatile memory module. The at least one non-volatile memory module, comprising one or more non-volatile memory chips, is configured as a secondary storage for the host computing device. The at least one channel controller is configured to ensure proper and efficient data transfer between a set of data buffers located in the FMD controller and the at least one non-volatile memory module.
摘要翻译： 描述了高性能闪存设备（FMD）。 根据本发明的一个示例性实施例，高性能FMD包括I / O接口，FMD控制器以及至少一个非易失性存储器模块以及对应的至少一个通道控制器。 I / O接口被配置为将高性能FMD连接到主机计算设备FMD控制器被配置为控制主计算设备和主计算设备之间的数据传输（例如，数据读取，数据写入/编程和数据擦除）操作 非易失性内存模块。 包括一个或多个非易失性存储器芯片的至少一个非易失性存储器模块被配置为主计算设备的辅助存储器。 至少一个通道控制器被配置为确保位于FMD控制器和至少一个非易失性存储器模块中的一组数据缓冲器之间的适当和有效的数据传输。
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公开(公告)号：US20080195798A1
公开(公告)日：2008-08-14
申请号：US11932941
申请日：2007-10-31
CPC分类号： G06F12/1416 , G06F3/0664 , G06F3/0688 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： Non-volatile memory based computer systems and methods are described. According to one aspect of the invention, at least one non-volatile memory module is coupled to a computer system as main storage. The non-volatile memory module is controlled by a northbridge controller configured to control the non-volatile memory as main memory. The page size of the at least one non-volatile memory module is configured to be the size of one of the cache lines associated with a microprocessor of the computer system. According to another aspect, at least one non-volatile memory module is coupled to a computer system as data read/write buffer of one or more hard disk drives. The non-volatile memory module is controlled by a southbridge controller configured to control the non-volatile memory as an input/out device. The page size of the at least one non-volatile memory module is configured in proportion to characteristics of the hard disk drives.
摘要翻译： 描述了基于非易失性存储器的计算机系统和方法。 根据本发明的一个方面，至少一个非易失性存储器模块耦合到作为主存储器的计算机系统。 非易失性存储器模块由配置成将非易失性存储器控制为主存储器的北桥控制器来控制。 至少一个非易失性存储器模块的页面大小被配置为与计算机系统的微处理器相关联的高速缓存行之一的大小。 根据另一方面，至少一个非易失性存储器模块作为一个或多个硬盘驱动器的数据读/写缓冲器耦合到计算机系统。 非易失性存储器模块由配置成将非易失性存储器控制为输入/输出设备的南桥控制器来控制。 至少一个非易失性存储器模块的页面大小被配置成与硬盘驱动器的特性成比例。
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5.发明申请Portable Electronic Storage Devices with Hardware Security Based on Advanced Encryption Standard 审中-公开基于高级加密标准的硬件安全便携式电子存储设备公开(公告)号：US20080192928A1
公开(公告)日：2008-08-14
申请号：US11924448
申请日：2007-10-25
CPC分类号： G06F12/1416 , G06F21/78 , G06F21/85 , G06F2221/2107 , G06K19/07 , G06K19/07354 , G07C9/00087 , H04L9/0631 , H04L9/0894 , H04L9/3228 , H04L2209/34
摘要： Portable electronic storage devices with hardware based security are described. According to one exemplary embodiment of the present invention, a portable electronic storage device (PESD) comprises a security engine integrated thereon. The security engine is configured to provide data encryption, data decryption, and encryption/decryption key (referred to as a key) generation according to a security standard (e.g., Advance Encryption Standard (AES)). AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit data block is encrypted by transforming the data block in a unique way into a new data block of the same size. AES is symmetric sine the same key is used for encryption and the reverse transformation (i.e., decryption). The only secret necessary to keep for security is the key. AES may use different key-lengths (i.e., 128-bit, 192-bits and 256-bits).
摘要翻译： 描述了具有硬件安全性的便携式电子存储设备。 根据本发明的一个示例性实施例，便携式电子存储设备（PESD）包括集成在其上的安全引擎。 安全引擎被配置为根据安全标准（例如，高级加密标准（AES））提供数据加密，数据解密和加密/解密密钥（称为密钥）生成。 AES是一种对称加密算法，处理128位数据块。 在密钥的影响下，通过以独特的方式将数据块变换成相同大小的新数据块来加密128位数据块。 AES是对称正弦，相同的密钥用于加密和反向转换（即解密）。 保护安全所必需的唯一秘密就是关键。 AES可以使用不同的密钥长度（即128位，192位和256位）。
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公开(公告)号：US08019943B2
公开(公告)日：2011-09-13
申请号：US13089898
申请日：2011-04-19
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/214 , G06F2212/7208 , G11C2211/5641
摘要： High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.
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7.发明授权Non-volatile memory device manufacturing process testing systems and methods thereof 失效非易失性存储器件制造工艺测试系统及其方法公开(公告)号：US07802155B2
公开(公告)日：2010-09-21
申请号：US12042316
申请日：2008-03-04
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C5/04 , G11C16/04 , G11C2029/0409
摘要： Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.
摘要翻译： 描述了制造和测试非易失性存储器（NVM）器件的系统和方法。 根据一个示例性实施例，在制造NVM模块期间的功能测试是通过包括计算机和经由外部总线耦合到计算机的NVM测试仪的系统进行的。 NVM测试仪包括多个槽。 每个插槽被配置为容纳待测试的相应的一个NVM模块。 NVM测试器被配置为包括输入/输出接口，具有相关联的RAM和ROM的微控制器，数据发生器，地址发生器，比较器，比较状态存储空间，测试结果指示器和NVM模块检测器。 数据发生器产生可重复的数据位序列作为测试向量。 已知的测试向量写入被测NVM模块的NVM。 然后将已知的测试向量与从NVM模块检索的数据进行比较。
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8.发明授权Memory address management systems in a large capacity multi-level cell (MLC) based flash memory device 有权大容量多级单元（MLC）闪存设备中的内存地址管理系统公开(公告)号：US08015348B2
公开(公告)日：2011-09-06
申请号：US12980591
申请日：2010-12-29
IPC分类号： G06F12/08
CPC分类号： H05K1/182 , G06F12/00 , H01R13/447 , H05K1/181 , H05K5/0278 , H05K2201/10189 , H05K2201/10446 , H05K2203/1572
摘要： Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.
摘要翻译： 描述了在大容量多级基于单元的闪存设备中管理存储器地址的方法和系统。 根据一个方面，一种闪存设备包括一个使用索引方案来管理逻辑到物理地址相关的处理单元。 闪存被分为N组。 每个集合包括多个条目（即，块）。 对于物理块号和相关联的页面使用信息（以下称为“PLTPPUI”）的N组部分逻辑条目号被存储在基于MLC的闪速存储器的保留区域中。 只有一个N集被加载以寻址相关和页面使用存储器（ACPUM），这是一个有限大小的随机存取存储器（RAM）。 在一个实施例中，静态RAM（SRAM）被实现用于地址相关的快速访问时间。 与数据传输请求一起接收的LSA指示将N组PLTPPUI中的哪一个加载到ACPUM中。
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9.发明申请公开(公告)号：US20080320209A1
公开(公告)日：2008-12-25
申请号：US12141879
申请日：2008-06-18
CPC分类号： G06F13/161 , G06F12/0246 , G06F2212/7201 , G06F2212/7203
摘要： High performance and endurance non-volatile memory (NVM) based storage systems are disclosed. According to one aspect of the present invention, a NVM based storage system comprises at least one intelligent NVM device. Each intelligent NVM device includes a control interface logic and NVM. Logical-to-physical address conversion is performed within the control interface logic, thereby eliminating the need of address conversion in a storage system level controller. In another aspect, a volatile memory buffer together with corresponding volatile memory controller and phase-locked loop circuit is included in a NVM based storage system. The volatile memory buffer is partitioned to two parts: a command queue; and one or more page buffers. The command queue is configured to hold received data transfer commands by the storage protocol interface bridge, while the page buffers are configured to hold data to be transmitted between the host computer and the at least one NVM device.
摘要翻译： 公开了基于高性能和耐久性非易失性存储器（NVM）的存储系统。 根据本发明的一个方面，一种基于NVM的存储系统包括至少一个智能NVM设备。 每个智能NVM设备都包括一个控制接口逻辑和NVM。 在控制接口逻辑中执行逻辑到物理地址转换，从而消除了存储系统级控制器中地址转换的需要。 在另一方面，在基于NVM的存储系统中包括易失性存储器缓冲器以及相应的易失性存储器控制器和锁相环电路。 易失性存储缓冲区分为两部分：命令队列; 和一个或多个页面缓冲区。 命令队列被配置为通过存储协议接口桥保存接收到的数据传输命令，而页缓冲器被配置为保存要在主计算机和至少一个NVM设备之间传输的数据。
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10.发明申请Non-Volatile Memory Device Manufacturing Process Testing Systems and Methods Thereof 失效非易失性存储器件制造工艺测试系统及其方法公开(公告)号：US20080201622A1
公开(公告)日：2008-08-21
申请号：US12042316
申请日：2008-03-04
CPC分类号： G11C29/56 , G11C5/04 , G11C16/04 , G11C2029/0409
摘要： Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.
摘要翻译： 描述了制造和测试非易失性存储器（NVM）器件的系统和方法。 根据一个示例性实施例，在制造NVM模块期间的功能测试是通过包括计算机和经由外部总线耦合到计算机的NVM测试仪的系统进行的。 NVM测试仪包括多个槽。 每个插槽被配置为容纳待测试的相应的一个NVM模块。 NVM测试器被配置为包括输入/输出接口，具有相关联的RAM和ROM的微控制器，数据发生器，地址发生器，比较器，比较状态存储空间，测试结果指示器和NVM模块检测器。 数据发生器产生可重复的数据位序列作为测试向量。 已知的测试向量写入被测NVM模块的NVM。 然后将已知的测试向量与从NVM模块检索的数据进行比较。
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