DIGITAL IMAGE PROCESSING APPARATUS INCLUDING HANDSHAKE CORRECTION MODULE AND METHODS OF CONTROLLING THE DIGITAL IMAGE PROCESSING APPARATUS
    51.
    发明申请
    DIGITAL IMAGE PROCESSING APPARATUS INCLUDING HANDSHAKE CORRECTION MODULE AND METHODS OF CONTROLLING THE DIGITAL IMAGE PROCESSING APPARATUS 有权
    数字图像处理装置,包括汉字修正模块和数字图像处理装置的控制方法

    公开(公告)号:US20120162455A1

    公开(公告)日:2012-06-28

    申请号:US13157444

    申请日:2011-06-10

    IPC分类号: H04N5/228

    CPC分类号: H04N5/2328 H04N5/225

    摘要: A digital image processing apparatus and a method of controlling the digital image processing apparatus, the method including: generating a live view image; performing a preprocessing operation on the live view image; driving a vibration mode of a handshake correction module in response to a result of the preprocessing operation; and if a photographing signal is input, generating a photographing image after terminating the vibration mode of the handshake correction module.

    摘要翻译: 一种数字图像处理装置和数字图像处理装置的控制方法,该方法包括:生成实时取景图像; 对实时取景图像执行预处理操作; 响应于预处理操作的结果驱动握手校正模块的振动模式; 并且如果输入了拍摄信号,则在终止了握手校正模块的振动模式之后生成拍摄图像。

    Jig and vacuum equipment for surface adhesion and adhesion method using the vacuum operative adhesion
    52.
    发明申请
    Jig and vacuum equipment for surface adhesion and adhesion method using the vacuum operative adhesion 审中-公开
    夹具和真空设备的表面粘附和粘附方法使用真空操作粘合

    公开(公告)号:US20070031997A1

    公开(公告)日:2007-02-08

    申请号:US11499370

    申请日:2006-08-04

    IPC分类号: H01L21/00

    CPC分类号: H01L21/67363

    摘要: Provided is a jig which can be used in a process of adhering a adhering object to a to-be adhered object in a vacuum atmosphere, and vacuum equipment for use in the adhering process. The jig includes a first frame and a second frame which together define a chamber for receiving the first and second objects. The first frame includes a seating portion having a plurality of seating pockets, and an actuator disposed below each of the seating pockets, the actuator being movable with respect to the seating pockets. A first elastic member is disposed in the jig below the actuator. The first elastic member being positioned such that it can contact and move the actuator in response to a change of pressure in the jig chamber. The second frame includes a second elastic member which is positioned adjacent to each of the seating pockets. The second elastic member being movable to the change of pressure in the jig chamber.

    摘要翻译: 提供了一种夹具,其可用于在真空气氛中将粘附物粘附到待粘合物体的过程中,以及用于粘合过程的真空设备。 夹具包括第一框架和第二框架,第一框架和第二框架共同限定用于接收第一和第二物体的室。 第一框架包括具有多个座舱的座位部分和设置在每个座舱下方的致动器,所述致动器可相对于所述座舱口移动。 第一弹性构件设置在致动器下方的夹具中。 第一弹性构件被定位成使得其可以响应于夹具室中的压力变化而接触和移动致动器。 第二框架包括第二弹性构件,该第二弹性构件邻近每个座舱口定位。 第二弹性构件可移动到夹具室中的压力变化。

    MOS transistors having inverted T-shaped gate electrodes
    53.
    发明授权
    MOS transistors having inverted T-shaped gate electrodes 失效
    MOS晶体管具有倒置的T形栅电极

    公开(公告)号:US07154154B2

    公开(公告)日:2006-12-26

    申请号:US10683782

    申请日:2003-10-10

    IPC分类号: H01L29/76

    摘要: MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.

    摘要翻译: MOS晶体管具有限定在半导体衬底的一部分中的有源区,有源区上的栅电极和衬底中的漏极和源极区。 第一和第二横向突起从栅电极的相应侧壁的下部延伸。 漏极区域在第一横向突起下方具有第一轻掺杂漏极区域,与第一轻掺杂漏极区域相邻的第二轻掺杂漏极区域和与第二轻掺杂漏极区域相邻的重掺杂漏极区域。 源极区域类似地在第二横向突起下方具有第一轻掺杂源极区域,与第一轻掺杂源极区域相邻的第二轻掺杂源极区域和与第二轻掺杂源极区域相邻的重掺杂源极区域 。 第二轻掺杂区域比第一轻掺杂区域深,并且栅电极可以具有倒置T形。

    Anti-static adhesive composition, polarizing plate and surface protective film using the composition
    56.
    发明授权
    Anti-static adhesive composition, polarizing plate and surface protective film using the composition 有权
    防静电胶组合物,偏光板及表面保护膜采用组合物

    公开(公告)号:US08187680B2

    公开(公告)日:2012-05-29

    申请号:US12937838

    申请日:2009-04-15

    IPC分类号: C09K19/00

    摘要: Disclosed are an anti-static adhesive composition, and a polarizing plate and/or a surface protective film fabricated using the same. More particularly, an anti-static adhesive composition for imparting enhanced anti-static properties, including a metal salt represented by Formula 1 as an anti-static agent so as to sufficiently inhibit generation of static electricity while not deteriorating inherent physical properties of an adhesive such as adhesiveness, durability and reliability, etc., is provided. In addition, a polarizing plate and and/or a surface protective film fabricated using the foregoing anti-static adhesive composition are provided. M+[(FSO2)2N]−  (Formula 1) wherein M is an alkali metal.

    摘要翻译: 公开了防静电粘合剂组合物,以及使用其制造的偏振片和/或表面保护膜。 更具体地,涉及一种用于赋予抗静电性能的抗静电粘合剂组合物,包括由式1表示的金属盐作为防静电剂,以充分抑制静电产生,同时不会降低粘合剂的固有物理性能 提供了粘合性,耐久性和可靠性等。 此外,提供了使用上述防静电粘合剂组合物制造的偏振片和/或表面保护膜。 M + [(FSO 2)2 N] - (式1)其中M为碱金属。

    Semiconductor device having bar type active pattern
    57.
    发明授权
    Semiconductor device having bar type active pattern 有权
    具有棒式有源图案的半导体器件

    公开(公告)号:US08106464B2

    公开(公告)日:2012-01-31

    申请号:US12461500

    申请日:2009-08-13

    IPC分类号: H01L27/088

    摘要: A semiconductor device having a bar type active pattern and a method of manufacturing the same are provided. The semiconductor device may include a semiconductor substrate having a semiconductor fin configured to protrude from a surface of the semiconductor substrate in a first direction, the semiconductor substrate having a first width and a second width crossing the first width, wherein the first width and the second width extend in a second direction. A plurality of active patterns may be arranged in the first direction with a separation gap from the semiconductor fin. A plurality of support patterns may be arranged between the semiconductor fin and one of the plurality of active patterns arranged closer to the semiconductor fin in the first direction, and between the plurality of active patterns arranged in the first direction to support the plurality of active patterns. A gate may be arranged to cross the plurality of active patterns in the second direction and to cover a portion of the at least one of the plurality of active patterns.

    摘要翻译: 提供了具有条形有源图案的半导体器件及其制造方法。 半导体器件可以包括具有半导体鳍片的半导体衬底,半导体鳍片被配置为在第一方向上从半导体衬底的表面突出,半导体衬底具有与第一宽度交叉的第一宽度和第二宽度,其中第一宽度和第二宽度 宽度在第二方向上延伸。 多个有源图案可以在第一方向上与半导体鳍片分离间隙布置。 多个支撑图案可以布置在半导体翅片与沿着第一方向布置得更靠近半导体鳍片的多个有源图案中的一个之间以及沿着第一方向布置的多个有源图案之间,以支撑多个有源图案 。 栅极可以布置成在第二方向上跨越多个有源图案并且覆盖多个有源图案中的至少一个的一部分。

    MOS field effect transistor having plurality of channels
    60.
    发明授权
    MOS field effect transistor having plurality of channels 有权
    MOS场效应晶体管具有多个通道

    公开(公告)号:US07795687B2

    公开(公告)日:2010-09-14

    申请号:US12538222

    申请日:2009-08-10

    IPC分类号: H01L29/76

    摘要: A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

    摘要翻译: 制造MOSFET的方法以自对准方式提供多个纳米线状通道。 根据该方法,在半导体衬底上依次形成第一材料层和半导体层。 在半导体层上形成第一掩模层图案,并且使用第一掩模层图案作为蚀刻掩模形成凹陷区域。 形成第一缩小的掩模层图案,并且在基板的表面上形成填充材料层。 形成一对第二掩模层图案,形成第一开口。 然后,蚀刻填充材料层以形成第二开口,去除暴露的第一材料层以暴露半导体层,并且形成包围暴露的半导体层的栅极绝缘层和栅极电极层。