公开(公告)号：US20130221426A1

公开(公告)日：2013-08-29

申请号：US13600616

申请日：2012-08-31

申请人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66719 ,  H01L29/7802 ,  H01L29/7811

摘要： A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

摘要翻译： 电力半导体装置的制造方法包括以下处理。 在第一导电类型的第二半导体层的表面中形成多个第一第二导电型杂质注入层。 在第一非注入区域和多个第一第二导电型杂质注入层中的一个之间形成第一沟槽。 形成第一导电类型的外延层并覆盖多个第一第二导电型杂质注入层。 在外延层的表面形成多个第二第二导电型杂质注入层。 在第二非注入区域和多个第二第二导电型杂质注入层中的一个之间形成第二沟槽。 形成第一导电类型的第三半导体层并且覆盖多个第二第二导电型杂质注入层。

公开(公告)号：US07759733B2

公开(公告)日：2010-07-20

申请号：US12055585

申请日：2008-03-26

申请人： Syotaro Ono ,  Wataru Saito

发明人： Syotaro Ono ,  Wataru Saito

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

摘要： A power semiconductor device includes: a first semiconductor substrate; a second semiconductor layer; a plurality of third semiconductor pillar regions and a plurality of fourth semiconductor pillar regions that are provided in an upper layer of the second semiconductor layer and alternatively arranged along a direction parallel to an upper surface of the first semiconductor substrate; a first main electrode; and a second main electrode. A concentration of first-conductivity-type impurity in a connective portion between the second semiconductor layer and the third semiconductor pillar regions is lower than concentrations of first-conductivity-type impurity in portions of both sides of the connective portion in a direction from the second semiconductor layer to the third semiconductor pillar regions.

摘要翻译： 功率半导体器件包括：第一半导体衬底; 第二半导体层; 多个第三半导体柱区域和多个第四半导体柱区域，其设置在所述第二半导体层的上层中，并且沿着与所述第一半导体衬底的上表面平行的方向交替布置; 第一主电极; 和第二主电极。 在第二半导体层和第三半导体柱区域之间的连接部分中的第一导电型杂质的浓度低于第二导电类型杂质在连接部分的两侧部分中的浓度 半导体层到第三半导体柱区域。

公开(公告)号：US07479678B2

公开(公告)日：2009-01-20

申请号：US11485284

申请日：2006-07-13

申请人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

发明人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734

摘要： A semiconductor element is provided, comprising a first semiconductor layer of the first conduction type; and a pillar layer including first semiconductor pillars of the first conduction type and second semiconductor pillars of the second conduction type arranged periodically and alternately on the first semiconductor layer. A semiconductor base layer of the second conduction type is formed on the upper surface of the pillar layer, And a second semiconductor layer of the first conduction type is formed on the upper surface of the semiconductor base layer. A control electrode of the trench gate type is formed in a trench, which is formed in depth through the semiconductor base layer to the first semiconductor pillar. The control electrode is tapered such that the width thereof decreases with the distance from a second main electrode toward a first main electrode and the tip thereof locates almost at the center of the first semiconductor pillar.

摘要翻译： 提供一种半导体元件，包括第一导电类型的第一半导体层; 以及第一导电型的第一半导体柱和第二导电型的第二半导体柱在第一半导体层上周期性且交替地配置的柱层。 第二导电类型的半导体基层形成在柱层的上表面上，第一导电类型的第二半导体层形成在半导体基层的上表面上。 沟槽栅型的控制电极形成在沟槽中，该沟槽通过半导体基底层向第一半导体柱形成深度。 控制电极是锥形的，使得其宽度随着从第二主电极朝向第一主电极的距离而减小，并且其尖端几乎位于第一半导体柱的中心。

公开(公告)号：US09093474B2

公开(公告)日：2015-07-28

申请号：US13600616

申请日：2012-08-31

申请人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66719 ,  H01L29/7802 ,  H01L29/7811

摘要： A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

摘要翻译： 电力半导体装置的制造方法包括以下处理。 在第一导电类型的第二半导体层的表面中形成多个第一第二导电型杂质注入层。 在第一非注入区域和多个第一第二导电型杂质注入层中的一个之间形成第一沟槽。 形成第一导电类型的外延层并覆盖多个第一第二导电型杂质注入层。 在外延层的表面形成多个第二第二导电型杂质注入层。 在第二非注入区域和多个第二第二导电型杂质注入层中的一个之间形成第二沟槽。 形成第一导电类型的第三半导体层并且覆盖多个第二第二导电型杂质注入层。

公开(公告)号：US20130248988A1

公开(公告)日：2013-09-26

申请号：US13607697

申请日：2012-09-08

申请人： Syotaro ONO ,  Wataru Saito ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

发明人： Syotaro ONO ,  Wataru Saito ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L21/02

CPC分类号： H01L29/7827 ,  H01L21/02697 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner.

摘要翻译： 半导体器件包括半导体衬底和多个栅电极，其包括在与半导体衬底平行的平面中沿第一方向延伸的部分。 所述半导体衬底具有包括多个第一导电型柱和第二导电型第二柱的第二半导体层，所述第二导电型柱和第二导电型第二柱设置在所述第一半导体层上，在与所述半导体衬底平行的平面中沿所述第一方向延伸，并且在第三方向上相交 具有与第一方向正交的第二方向，并且以交替的方式彼此相邻布置。

公开(公告)号：US20080246084A1

公开(公告)日：2008-10-09

申请号：US12055585

申请日：2008-03-26

申请人： Syotaro ONO ,  Wataru Saito

发明人： Syotaro ONO ,  Wataru Saito

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

摘要： A power semiconductor device includes: a first semiconductor substrate; a second semiconductor layer; a plurality of third semiconductor pillar regions and a plurality of fourth semiconductor pillar regions that are provided in an upper layer of the second semiconductor layer and alternatively arranged along a direction parallel to an upper surface of the first semiconductor substrate; a first main electrode; and a second main electrode. A concentration of first-conductivity-type impurity in a connective portion between the second semiconductor layer and the third semiconductor pillar regions is lower than concentrations of first-conductivity-type impurity in portions of both sides of the connective portion in a direction from the second semiconductor layer to the third semiconductor pillar regions.

摘要翻译： 功率半导体器件包括：第一半导体衬底; 第二半导体层; 多个第三半导体柱区域和多个第四半导体柱区域，其设置在所述第二半导体层的上层中，并且沿着与所述第一半导体衬底的上表面平行的方向交替布置; 第一主电极; 和第二主电极。 在第二半导体层和第三半导体柱区域之间的连接部分中的第一导电型杂质的浓度低于第二导电类型杂质在连接部分的两侧部分中的浓度 半导体层到第三半导体柱区域。

公开(公告)号：US20080237774A1

公开(公告)日：2008-10-02

申请号：US11864101

申请日：2007-09-28

申请人： Syotaro ONO ,  Wataru Saito

发明人： Syotaro ONO ,  Wataru Saito

IPC分类号： H01L29/66

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

摘要： A semiconductor device includes: a semiconductor substrate; a first semiconductor layer of a first conductivity type provided on a major surface of the semiconductor substrate and having lower doping concentration than the semiconductor substrate; a plurality of first semiconductor column regions of the first conductivity type provided on the first semiconductor layer;a plurality of second semiconductor column regions of a second conductivity type provided on the first semiconductor layer, the second semiconductor column regions being adjacent to the first semiconductor column regions; a first semiconductor region; a second semiconductor region; a gate insulating film; a first main electrode; a second main electrode; and a control electrode. Doping concentrations in both the first and second semiconductor column region are low on the near side of the first semiconductor layer and high on the second main electrode side.

摘要翻译： 半导体器件包括：半导体衬底; 第一导电类型的第一半导体层设置在半导体衬底的主表面上并且具有比半导体衬底低的掺杂浓度; 设置在第一半导体层上的多个第一导电类型的第一半导体柱区域; 设置在所述第一半导体层上的第二导电类型的多个第二半导体柱区域，所述第二半导体柱区域与所述第一半导体柱区域相邻; 第一半导体区域; 第二半导体区域; 栅极绝缘膜; 第一主电极; 第二主电极; 和控制电极。 第一和第二半导体柱区域中的掺杂浓度在第一半导体层的近侧为低，在第二主电极侧为高。

公开(公告)号：US07301202B2

公开(公告)日：2007-11-27

申请号：US11151410

申请日：2005-06-14

申请人： Shigeo Kouzuki ,  Hideki Okumura ,  Wataru Saito ,  Masaru Izumisawa ,  Masahiko Shiomi ,  Hitoshi Kobayashi ,  Kenichi Tokano ,  Satoshi Yanagisawa ,  Hironori Yoshioka ,  Manabu Kimura

发明人： Shigeo Kouzuki ,  Hideki Okumura ,  Wataru Saito ,  Masaru Izumisawa ,  Masahiko Shiomi ,  Hitoshi Kobayashi ,  Kenichi Tokano ,  Satoshi Yanagisawa ,  Hironori Yoshioka ,  Manabu Kimura

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/66712 ,  H01L29/7811

摘要： A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.

摘要翻译： 提供第一导电类型的半导体衬底作为用于多个功率MISFET单元的公共漏极。 在半导体衬底上形成中间半导体层，其杂质浓度低于半导体衬底的杂质浓度。 柱状区域形成在中间半导体层上，并且包括具有比中间半导体层的杂质浓度低的第一导电类型的半导体区域。

公开(公告)号：US20060138536A1

公开(公告)日：2006-06-29

申请号：US11151410

申请日：2005-06-14

申请人： Shigeo Kouzuki ,  Hideki Okumura ,  Wataru Saito ,  Masaru Izumisawa ,  Masahiko Shiomi ,  Hitoshi Kobayashi ,  Kenichi Tokano ,  Satoshi Yanagisawa ,  Hironori Yoshioka ,  Manabu Kimura

发明人： Shigeo Kouzuki ,  Hideki Okumura ,  Wataru Saito ,  Masaru Izumisawa ,  Masahiko Shiomi ,  Hitoshi Kobayashi ,  Kenichi Tokano ,  Satoshi Yanagisawa ,  Hironori Yoshioka ,  Manabu Kimura

IPC分类号： H01L29/76

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/66712 ,  H01L29/7811

摘要： A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.

摘要翻译： 提供第一导电类型的半导体衬底作为用于多个功率MISFET单元的公共漏极。 在半导体衬底上形成中间半导体层，其杂质浓度低于半导体衬底的杂质浓度。 柱状区域形成在中间半导体层上，并且包括具有比中间半导体层的杂质浓度低的第一导电类型的半导体区域。

公开(公告)号：US20050098826A1

公开(公告)日：2005-05-12

申请号：US11002638

申请日：2004-12-03

申请人： Masakazu Yamaguchi ,  Wataru Saito ,  Ichiro Omura ,  Masaru Izumisawa

发明人： Masakazu Yamaguchi ,  Wataru Saito ,  Ichiro Omura ,  Masaru Izumisawa

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/66712 ,  H01L29/7802

摘要： A method of manufacturing a semiconductor device in which a trench groove is formed in a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer is epitaxially grown so as to bury the trench groove. The second conductivity type semiconductor layer is then removed until a surface of the first conductivity type semiconductor layer is exposed. The first conductivity type semiconductor layer is epitaxially grown on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove. The first conductivity type semiconductor layer is selectively removed such that the second conductivity type semiconductor layer is exposed, and the epitaxially growing of the second conductivity type semiconductor layer is repeated through selectively removing the first conductivity type semiconductor layer.

摘要翻译： 一种制造半导体器件的方法，其中在第一导电类型半导体层中形成沟槽槽，并且外延生长第二导电类型半导体层以便埋入沟槽。 然后去除第二导电类型半导体层直到露出第一导电类型半导体层的表面。 在第一导电类型半导体层和第二导电类型半导体层上外延生长第一导电类型半导体层，使得第一导电类型半导体层的厚度增加与沟槽的深度基本相同的长度 。 选择性地去除第一导电型半导体层，使得露出第二导电类型半导体层，并且通过选择性地去除第一导电类型半导体层来重复第二导电类型半导体层的外延生长。