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公开(公告)号：US20070018243A1
公开(公告)日：2007-01-25
申请号：US11485284
申请日：2006-07-13
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/4236 , H01L29/66727 , H01L29/66734
摘要： A semiconductor element is provided, comprising a first semiconductor layer of the first conduction type; and a pillar layer including first semiconductor pillars of the first conduction type and second semiconductor pillars of the second conduction type arranged periodically and alternately on the first semiconductor layer. A semiconductor base layer of the second conduction type is formed on the upper surface of the pillar layer, And a second semiconductor layer of the first conduction type is formed on the upper surface of the semiconductor base layer. A control electrode of the trench gate type is formed in a trench, which is formed in depth through the semiconductor base layer to the first semiconductor pillar. The control electrode is tapered such that the width thereof decreases with the distance from a second main electrode toward a first main electrode and the tip thereof locates almost at the center of the first semiconductor pillar.
摘要翻译： 提供一种半导体元件，包括第一导电类型的第一半导体层; 以及第一导电型的第一半导体柱和第二导电型的第二半导体柱在第一半导体层上周期性且交替地配置的柱层。 第二导电类型的半导体基层形成在柱层的上表面上，第一导电类型的第二半导体层形成在半导体基层的上表面上。 沟槽栅型的控制电极形成在沟槽中，该沟槽通过半导体基底层向第一半导体柱形成深度。 控制电极是锥形的，使得其宽度随着从第二主电极朝向第一主电极的距离而减小，并且其尖端几乎位于第一半导体柱的中心。
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公开(公告)号：US07479678B2
公开(公告)日：2009-01-20
申请号：US11485284
申请日：2006-07-13
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/4236 , H01L29/66727 , H01L29/66734
摘要： A semiconductor element is provided, comprising a first semiconductor layer of the first conduction type; and a pillar layer including first semiconductor pillars of the first conduction type and second semiconductor pillars of the second conduction type arranged periodically and alternately on the first semiconductor layer. A semiconductor base layer of the second conduction type is formed on the upper surface of the pillar layer, And a second semiconductor layer of the first conduction type is formed on the upper surface of the semiconductor base layer. A control electrode of the trench gate type is formed in a trench, which is formed in depth through the semiconductor base layer to the first semiconductor pillar. The control electrode is tapered such that the width thereof decreases with the distance from a second main electrode toward a first main electrode and the tip thereof locates almost at the center of the first semiconductor pillar.
摘要翻译： 提供一种半导体元件，包括第一导电类型的第一半导体层; 以及第一导电型的第一半导体柱和第二导电型的第二半导体柱在第一半导体层上周期性且交替地配置的柱层。 第二导电类型的半导体基层形成在柱层的上表面上，第一导电类型的第二半导体层形成在半导体基层的上表面上。 沟槽栅型的控制电极形成在沟槽中，该沟槽通过半导体基底层向第一半导体柱形成深度。 控制电极是锥形的，使得其宽度随着从第二主电极朝向第一主电极的距离而减小，并且其尖端几乎位于第一半导体柱的中心。
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公开(公告)号：US07541643B2
公开(公告)日：2009-06-02
申请号：US11399448
申请日：2006-04-07
申请人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi
发明人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/402 , H01L29/41741 , H01L29/7811
摘要： This semiconductor device comprises a pillar layer including a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type formed alternately on a first semiconductor layer. At the same depth position in the device region and the end region, a difference between an impurity concentration [cm-3] of the second semiconductor pillar layer in the device region and that of the second semiconductor pillar layer in the end region is less than plus or minus 5%. A width W11 [um] of the first semiconductor pillar layer in the device region, a width W21 [um] of the second semiconductor pillar layer in the device region, a width W12 [um] of the first semiconductor pillar layer in the end region, and a width W22 [um] of the second semiconductor pillar layer in the end region, meet the relationship of W21/W11
摘要翻译： 该半导体器件包括：交替地在第一半导体层上形成的包括第一导电类型的第一半导体柱层和第二导电类型的第二半导体柱层的柱层。 在器件区域和端部区域的相同深度位置处，器件区域中的第二半导体柱层的杂质浓度[cm-3]与末端区域中的第二半导体柱层的杂质浓度[cm-3]之间的差小于 加或减5％。 器件区域中的第一半导体柱层的宽度W11 [μm]，器件区域中的第二半导体柱层的宽度W21 [μm]，端部区域中的第一半导体柱层的宽度W12 [μm] ，并且端部区域中的第二半导体柱层的宽度W22 [μm]满足W21 / W11
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公开(公告)号：US20060231917A1
公开(公告)日：2006-10-19
申请号：US11399448
申请日：2006-04-07
申请人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi
发明人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi
IPC分类号： H01L29/00
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/402 , H01L29/41741 , H01L29/7811
摘要： This semiconductor device comprises a pillar layer including a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type formed alternately on a first semiconductor layer. At the same depth position in the device region and the end region, a difference between an impurity concentration [cm-3] of the second semiconductor pillar layer in the device region and that of the second semiconductor pillar layer in the end region is less than plus or minus 5%. A width W11 [um] of the first semiconductor pillar layer in the device region, a width W21 [um] of the second semiconductor pillar layer in the device region, a width W12 [um] of the first semiconductor pillar layer in the end region, and a width W22 [um] of the second semiconductor pillar layer in the end region, meet the relationship of W21/W11
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公开(公告)号：US20080251838A1
公开(公告)日：2008-10-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
摘要翻译： 半导体器件包括：半导体衬底，至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽，其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层，以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极，其形成在所述半导体衬底上，以被分成多个部分，并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上，所述第一导电型源的端部 并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上， 以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。
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公开(公告)号：US20070194375A1
公开(公告)日：2007-08-23
申请号：US11674337
申请日：2007-02-13
IPC分类号： H01L29/94
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/7813
摘要： This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.
摘要翻译： 该半导体器件包括形成在第一半导体层表面上的第一导电类型的第一半导体层，第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。 第二导电类型的列层以一定间隔在基底层下的外延层中重复形成。 形成沟槽以穿透基底层以到达外延层; 并且栅电极经由栅极绝缘膜形成在沟槽中。 在基底层的周边的端部区域，在外延层上形成第二导电类型的端接层。 端接层形成为具有大于基底层的结深度的结深度。
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公开(公告)号：US07230297B2
公开(公告)日：2007-06-12
申请号：US11127224
申请日：2005-05-12
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译： 公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。
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公开(公告)号：US20060157778A1
公开(公告)日：2006-07-20
申请号：US11305202
申请日：2005-12-19
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0696
摘要： A power MOSFET includes an n-type drift layer and a p-type base layer formed in a layered manner on the n-type drift layer. Trench gates are formed to penetrate the p-type base layer to reach the n-type drift layer. On the p-type base layer, n+-type source regions and p+-type regions are formed. These n+-type source regions and p+-type regions are arranged alternately along a longitudinal direction of the trench gates. The n+-type source regions and the p+-type regions are arranged with a slant with respect to the longitudinal direction of the trench gates.
摘要翻译： 功率MOSFET包括在n型漂移层上分层形成的n型漂移层和p型基极层。 形成沟槽栅极以穿透p型基极层以到达n型漂移层。 在p型基底层上形成n + +型源区和p + + +型区。 这些n + + +型源极区域和p + + +区域沿沟槽栅极的纵向方向交替布置。 相对于沟槽栅极的纵向方向，n + P +型源极区域和p + H +型区域以倾斜的方式排列。
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公开(公告)号：US08049270B2
公开(公告)日：2011-11-01
申请号：US11924175
申请日：2007-10-25
IPC分类号： H01L29/732
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/41766
摘要： This semiconductor device an epitaxial layer of a first conductivity type formed on a surface of the first semiconductor layer, and a base layer of a second conductivity type formed on a surface of the epitaxial layer. A diffusion layer of a first conductivity type is selectively formed in the base layer, and a trench penetrates the base layer to reach the epitaxial layer. A gate electrode is formed in the trench through the gate insulator film formed on the inner wall of the trench. A first buried diffusion layer of a second conductivity type is formed in the epitaxial layer deeper than the bottom of the gate electrode. A second buried diffusion layer connects the first buried diffusion layer and the base layer and has a resistance higher than that of the first buried diffusion layer.
摘要翻译： 该半导体器件形成在第一半导体层的表面上的第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。 在基底层中选择性地形成第一导电类型的扩散层，并且沟槽穿透基底层以到达外延层。 通过形成在沟槽内壁上的栅极绝缘膜，在沟槽中形成栅电极。 在比栅电极的底部更深的外延层中形成第二导电类型的第一掩埋扩散层。 第二掩埋扩散层连接第一掩埋扩散层和基底层，并且具有比第一掩埋扩散层的电阻高的电阻。
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公开(公告)号：US07663186B2
公开(公告)日：2010-02-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a substrate, a surface portion thereof serving as a drain layer; a first main electrode connected to the drain layer; an epitaxial layer formed on the drain layer; a base layer formed on the epitaxial layer; a source layer formed in a base layer surface portion; an insulated trench sandwiched by base layers; a JFET layer formed on trench side walls; an LDD layer formed in a base layer surface portion and connected to the JFET layer around a top face of the trench; a control electrode formed on a gate insulating film formed on an LDD layer surface part, on surfaces of source layer end parts facing each other across the trench, and on a base layer region sandwiched by the LDD and source layers; and a second main electrode connected to the source and base layers sandwiching the control electrode.
摘要翻译： 半导体器件包括：衬底，用作漏极层的表面部分; 连接到漏极层的第一主电极; 形成在漏极层上的外延层; 形成在外延层上的基底层; 形成在基层表面部分中的源极层; 由基层夹住的绝缘沟槽; 形成在沟槽侧壁上的JFET层; LDD层，其形成在基底表面部分中并且围绕所述沟槽的顶面连接到所述JFET层; 形成在形成在LDD层表面部分上的栅极绝缘膜上的控制电极，在沟槽之间彼此面对的源极层部分的表面上以及由LDD和源极层夹持的基极层区域; 以及连接到夹持控制电极的源极和基极层的第二主电极。
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