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68 条记录 (耗时 0.027 秒)

    Low dropout regulator and related method
    52.
    发明授权
    Low dropout regulator and related method 有权

    公开(公告)号：US09977441B2

    公开(公告)日：2018-05-22

    申请号：US15093211

    申请日：2016-04-07

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chung-Cheng Chou ,  Po-Hao Lee

    IPC分类号： G05F1/46 ,  G05F1/575 ,  H02M1/12 ,  H02M3/338

    CPC分类号： G05F1/468 ,  G05F1/46 ,  G05F1/575 ,  H02M1/12 ,  H02M3/3382

    摘要： A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.

    Integration of Magneto-Resistive Random Access Memory and Capacitor
    54.
    发明申请
    Integration of Magneto-Resistive Random Access Memory and Capacitor 审中-公开
    磁阻随机存取存储器和电容器的集成

    公开(公告)号：US20140264463A1

    公开(公告)日：2014-09-18

    申请号：US14066978

    申请日：2013-10-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chung-Cheng Chou ,  Ya-Chen Kao ,  Tien-Wei Chiang

    IPC分类号： H01L27/22 ,  H01L43/12

    CPC分类号： H01L27/228 ,  H01L43/10 ,  H01L43/12

    摘要： The present disclosure provides one embodiment of a semiconductor structure that includes a first metal layer formed on a semiconductor substrate, wherein the first metal layer includes a first metal feature in a first region and a second metal feature in a second region; a second metal layer disposed on the first metal layer, wherein the second metal layer includes a third metal feature in the first region and a fourth metal feature in a second region; a magneto-resistive memory device sandwiched between the first metal feature and the third metal feature; and a capacitor sandwiched between the second metal feature and the fourth metal feature.

    摘要翻译： 本公开提供了半导体结构的一个实施例，其包括形成在半导体衬底上的第一金属层，其中第一金属层包括第一区域中的第一金属特征和第二区域中的第二金属特征; 设置在所述第一金属层上的第二金属层，其中所述第二金属层包括所述第一区域中的第三金属特征和在第二区域中的第四金属特征; 夹在所述第一金属特征和所述第三金属特征之间的磁阻存储器件; 以及夹在第二金属特征和第四金属特征之间的电容器。