Timing for IC chip
    52.
    发明授权

    公开(公告)号:US10142095B2

    公开(公告)日:2018-11-27

    申请号:US15334979

    申请日:2016-10-26

    Abstract: A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.

    Synchronization in FMCW Radar Systems
    54.
    发明申请

    公开(公告)号:US20170299693A1

    公开(公告)日:2017-10-19

    申请号:US15635659

    申请日:2017-06-28

    Abstract: The disclosure provides a radar apparatus for estimating a position and a velocity of the plurality of obstacles. The radar apparatus includes a local oscillator that generates a first signal. A first transmit unit receives the first signal from the local oscillator and generates a first transmit signal. A frequency shifter receives the first signal from the local oscillator and generates a second signal. A second transmit unit receives the second signal and generates a second transmit signal. The frequency shifter provides a frequency offset to the first signal based on a routing delay mismatch to generate the second signal such that the first transmit signal is phase coherent with the second transmit signal.

    Linear approximation of a complex number magnitude

    公开(公告)号:US12260187B2

    公开(公告)日:2025-03-25

    申请号:US17357919

    申请日:2021-06-24

    Abstract: A device includes a comparison circuit and a calculation circuit coupled to the comparison circuit. The comparison circuit is configured to receive a first digital input value (X) and a second digital input value (Y), and provide a first digital output value that indicates one of a first relationship, a second relationship, and a third relationship between X and Y. The calculation circuit is configured to receive X and Y, receive the first digital output value, and provide a second digital output value. The second digital output value is a first linear combination of X and Y responsive to the first digital output value indicating the first relationship, a second linear combination of X and Y responsive to the first digital output value indicating the second relationship, and a third linear combination of X and Y responsive to the first digital output value indicating the third relationship.

    On-field phase calibration
    58.
    发明授权

    公开(公告)号:US12235347B2

    公开(公告)日:2025-02-25

    申请号:US18502445

    申请日:2023-11-06

    Abstract: A radar transceiver includes a phase shifter that is controlled to apply an induced phase shift in a first subset of chirp signals of a frame of chirp signals, which also includes a second subset of chirp signals in which no phase shift is applied. Other circuitry generates digital signals based on received reflected signals, which are based on transmitted signals. Processing circuitry performs a Fast Fourier Transform (FFT) on a first subset of digital signals, corresponding to the first subset of chirp signals, to generate a first range-Doppler array, and performs a FFT on the second subset of digital signals, corresponding to the second subset of chirp signals, to generate a second range-Doppler array; identifies peaks in the first and second range-Doppler arrays to detect an object; and compares a phases of peaks at corresponding positions in the first and second range-Doppler arrays to determine a measured phase shift between the two peaks.

    Non-active chirp dithering in FMCW radar

    公开(公告)号:US11874392B2

    公开(公告)日:2024-01-16

    申请号:US17498342

    申请日:2021-10-11

    CPC classification number: G01S7/2813 G01S7/352

    Abstract: A non-transitory computer-readable storage device stores machine instructions which, when executed by a processor, cause the processor to determine a chirp period Tc for radar chirps in a radar frame. The chirp period Tc comprises a rising period Trise and a falling period Tfall. The processor determines, for each radar chirp in the radar frame, a corresponding randomized frequency characteristic during Tfall, and causes a radar sensor circuit to generate the radar chirps in the radar frame based on Tc, Trise, Tfall, and the corresponding randomized frequency characteristics. In some implementations, the machine instructions to determine the corresponding randomized frequency characteristic comprise machine instructions to determine a frequency step having a frequency f_step and a period Tstep. At least one of the frequency f_step and the period Tstep is dithered across radar chirps in the radar frame.

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