公开(公告)号：US20220155692A1

公开(公告)日：2022-05-19

申请号：US17665757

申请日：2022-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Dong-Yo Jheng ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Chih-Jie Lee ,  Shuo-Yen Chou ,  Ru-Gun Liu

IPC: G03F7/20 ,  G03F1/36

Abstract: A method includes receiving a layout for fabricating a mask, determining a first target contour corresponding to a first set of process conditions, determining a second target contour corresponding to a second set of process conditions, simulating a first potential modification to the layout under the first set of process conditions to generate a first simulated contour, simulating a second potential modification to the layout under the second set of process conditions to generate a second simulated contour, evaluating costs of the first and second potential modifications based on comparing the first and second simulated contours to the first and second target contours, respectively, and providing the layout and one of the first and second potential modifications having a lower cost for fabricating the mask. The first set of process conditions is different from the second set of process conditions.

公开(公告)号：US11322393B2

公开(公告)日：2022-05-03

申请号：US17120989

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Nien Su ,  Shu-Huei Suen ,  Jyu-Horng Shieh ,  Ru-Gun Liu

IPC: H01L21/76 ,  H01L21/31 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/263

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

公开(公告)号：US11243472B2

公开(公告)日：2022-02-08

申请号：US16895547

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Dong-Yo Jheng ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Chih-Jie Lee ,  Shuo-Yen Chou ,  Ru-Gun Liu

IPC: G06F30/33 ,  G03F7/20 ,  G03F1/36

Abstract: A method includes receiving a layout that includes a shape to be formed on a photomask and determining a plurality of target lithographic contours for the shape, wherein the plurality of target lithographic contours includes a first target lithographic contour for a first set of process conditions and a second target lithographic contour for a second set of process conditions, performing a lithographic simulation of the layout to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions, determining a first edge placement error between the first simulated contour and the first target lithographic contour and a second edge placement error between the second simulated contour and the second target lithographic contour, and determining a modification to the layout based on the first edge placement error and the second edge placement error.

公开(公告)号：US11201064B2

公开(公告)日：2021-12-14

申请号：US16894545

申请日：2020-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Min Hsiao ,  Chien-Wen Lai ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Wei-Shuo Su ,  Yu-Chen Chang

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/027

Abstract: A four signal line unit cell is formed on a substrate using a combination of an extreme ultraviolet photolithography process and one or more self aligned deposition processes. The photolithography process and the self aligned deposition processes result in spacers on a hard mask above the substrate. The spacers define a pattern of signal lines to be formed on the substrate for a unit cell. The photolithography process and self aligned deposition processes result in signal lines having a critical dimension much smaller than features that can be defined by the extreme ultraviolet photolithography process.

公开(公告)号：US11175597B2

公开(公告)日：2021-11-16

申请号：US16697138

申请日：2019-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Ming Chang ,  Chiu-Hsiang Chen ,  Ru-Gun Liu ,  Minfeng Chen

IPC: G03F7/20 ,  G03F1/64

Abstract: A lithography patterning system includes a reticle having patterned features, a pellicle having a plurality of openings, a radiation source configured for emitting radiation to reflect and/or project the patterned features, and one or more mirrors configured for guiding reflected and/or projected patterned features onto a wafer. The pellicle is configured to protect the reticle against particles and floating contaminants. The plurality of openings include between 5% and 99.9% of lateral surface area of the pellicle. The pellicle can be attached to the reticle on a side of the patterned features, placed beside an optical path between the radiation source and the wafer, or placed in an optical path between mirrors and the radiation source. The plurality of openings in the pellicle are formed by a plurality of bar shaped materials, or formed in a honey comb structure or a mesh structure.

公开(公告)号：US11106140B2

公开(公告)日：2021-08-31

申请号：US16512767

申请日：2019-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Ming Chang ,  Chiu-Hsiang Chen ,  Ru-Gun Liu

IPC: G03F7/20

Abstract: A method for taking heat away from the photomask includes driving a working fluid to flow between a photomask and a fluid retaining structure and through a first slit of the fluid retaining structure, such that a boundary of the working fluid is confined between the photomask and the fluid retaining structure; and generating a light to irradiate the photomask through a light transmission region of the fluid retaining structure.

公开(公告)号：US11088030B2

公开(公告)日：2021-08-10

申请号：US15157200

申请日：2016-05-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jui-Yao Lai ,  Ru-Gun Liu ,  Sai-Hooi Yeong ,  Yen-Ming Chen ,  Yung-Sung Yen ,  Ying-Yan Chen

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417 ,  H01L23/535

Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.

公开(公告)号：US20210242212A1

公开(公告)日：2021-08-05

申请号：US17234256

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Guo-Huei Wu ,  Yu-Jung Chang

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US11080458B2

公开(公告)日：2021-08-03

申请号：US16584396

申请日：2019-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu An Tien ,  Hsu-Ting Huang ,  Ru-Gun Liu ,  Shih-Hsiang Lo

IPC: G06F30/30 ,  G06F30/398 ,  G03F7/20 ,  G01N21/95 ,  G03F1/36 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/20 ,  G06F119/18 ,  G03F1/70

Abstract: In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.

公开(公告)号：US11063005B2

公开(公告)日：2021-07-13

申请号：US16682377

申请日：2019-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou Sio ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Chi-Yeh Yu ,  Jiann-Tyng Tzeng ,  Ru-Gun Liu ,  Wen-Hao Chen

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/485 ,  H01L21/8234 ,  H01L23/532

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first conductive interconnect wire extending in a first direction over a substrate. A second conductive interconnect wire is arranged over the first conductive interconnect wire. A via rail is configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire. The first conductive interconnect wire and the second conductive interconnect wire extend as continuous structures past one or more sides of the via rail.