公开(公告)号：US08989581B2

公开(公告)日：2015-03-24

申请号：US13427754

申请日：2012-03-22

申请人： Inwoong Kim ,  Paparao Palacharla ,  Xi Wang ,  Motoyoshi Sekiya

发明人： Inwoong Kim ,  Paparao Palacharla ,  Xi Wang ,  Motoyoshi Sekiya

IPC分类号： H04J14/02 ,  H04B10/572

CPC分类号： H04B10/572

摘要： An optical network for reassigning a carrier wavelength of an optical signal may include first and second optical nodes. The first optical node may be configured to transmit an optical signal along an optical path. The first optical node may also be configured to tune a carrier wavelength of the optical signal from a first wavelength to a second wavelength, according to a continuous function, to reassign the carrier wavelength of the optical signal. The second optical node may be configured to receive the optical signal and may include a feedback loop configured to adjust a wavelength of a reference optical signal to approximate the carrier wavelength of the optical signal.

摘要翻译： 用于重新分配光信号的载波波长的光网络可以包括第一和第二光节点。 第一光节点可以被配置为沿着光路传输光信号。 第一光节点还可以被配置为根据连续功能将光信号的载波波长从第一波长调谐到第二波长，以重新分配光信号的载波波长。 第二光节点可以被配置为接收光信号，并且可以包括被配置为调整参考光信号的波长以近似光信号的载波波长的反馈回路。

公开(公告)号：US20130054209A1

公开(公告)日：2013-02-28

申请号：US13696437

申请日：2011-09-25

申请人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Zhan Chai ,  Xi Wang

发明人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Zhan Chai ,  Xi Wang

IPC分类号： G06F17/10

CPC分类号： G06F17/5036

摘要： The present invention provides a modeling method of a SPICE model series of a Silicon On Insulator (SOI) Field Effect Transistor (FET), where auxiliary devices are designed and fabricated, electrical property data is measured, intermediate data is obtained, model parameters are extracted based on the intermediate data, a SPICE model of an SOI FET of a floating structure is established, model parameters are extracted by using the intermediate data and data of the auxiliary devices, a macro model is complied, and a SPICE model of an SOI FET of a body leading-out structure is established. The modeling method provided in the present invention takes an influence of a parasitic transistor of a leading-out part in a body leading-out structure into consideration, and model series established by using the method can more accurately reflect actual operating conditions and electrical properties of the SOI FET of a body leading-out structure and the SOI FET of a floating structure, thereby improving fitting effects of the models.

摘要翻译： 本发明提供了一种在绝缘体上硅（SOI）场效应晶体管（FET）的SPICE模型系列的建模方法，其中设计和制造辅助装置，测量电性能数据，获得中间数据，提取模型参数 基于中间数据，建立了浮动结构的SOI FET的SPICE模型，通过使用辅助设备的中间数据和数据，宏模型以及SOI FET的SPICE模型来提取模型参数 建立了身体导出结构。 本发明提供的建模方法考虑了体导出结构中的导出部分的寄生晶体管的影响，并且通过使用该方法建立的模型系列可以更准确地反映实际的操作条件和电气特性 主体引出结构的SOI FET和浮动结构的SOI FET，从而提高了模型的拟合效果。

公开(公告)号：US08346965B2

公开(公告)日：2013-01-01

申请号：US12942586

申请日：2010-11-09

申请人： Qiong Zhang ,  Paparao Palacharla ,  Qingya She ,  Xi Wang ,  Motoyoshi Sekiya

发明人： Qiong Zhang ,  Paparao Palacharla ,  Qingya She ,  Xi Wang ,  Motoyoshi Sekiya

IPC分类号： G06F15/16

CPC分类号： H04J14/0257 ,  H04J14/0212

摘要： A method may include constructing an auxiliary graph for a network comprising a plurality of network elements, the network elements having an Internet Protocol layer, a lower layer, and a wavelength layer, the auxiliary graph including a plurality of directed edges, the plurality of directed edges indicative of connectivity of components of the plurality of network elements. The method may further include: (i) deleting directed edges from the auxiliary graph whose available bandwidth is lower than the required bandwidth of a selected demand; (ii) finding a path for the demand on the auxiliary graph via remaining directed edges; (iii) deleting at least one directed edge of the auxiliary graph on the wavelength layer along the path; (iv) adding lower layer lightpath edges to the auxiliary graph for a lower layer lightpath for the path; and (v) converting lower layer lightpaths to Internet Protocol lightpaths if a conversion condition is satisfied.

摘要翻译： 方法可以包括为包括多个网络元件的网络构建辅助图形，所述网络元件具有互联网协议层，下层和波长层，所述辅助图形包括多个有向边缘，所述多个定向 指示多个网络元件的组件的连接性的边缘。 该方法还可以包括：（i）从可用带宽低于所选择的需求的所需带宽的辅助图中删除有向边; （ii）通过剩余的有向边找到对辅助图的需求的路径; （iii）沿所述路径删除所述波长层上的辅助图形的至少一个有向边缘; （iv）将下层光路边缘添加到辅助图形，用于路径的下层光路; 和（v）如果满足转换条件，则将下层光路转换为因特网协议光路。

公开(公告)号：US08330229B2

公开(公告)日：2012-12-11

申请号：US12810740

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC分类号： H01L27/092

CPC分类号： H01L27/1211 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/78696

摘要： A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Si (110) and p-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have different orientation channels, the GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, and prevent polysilicon gate depletion and short channel effects.

摘要翻译： 混合取向反转模式GAA（Gate-All-Around）CMOSFET包括具有第一通道的PMOS区域，具有第二通道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由n型Si（110）和p型Si（100）形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 根据本发明的装置结构相当简单，紧凑且高度集成。 在反转模式中，器件具有不同的取向通道，GAA结构具有跑道形，高k栅介质层和金属栅极，从而实现高载流子迁移率，并防止多晶硅栅极耗尽和短沟道效应。

公开(公告)号：US20120112283A1

公开(公告)日：2012-05-10

申请号：US13002303

申请日：2010-12-16

申请人： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

发明人： Xiaolu Huang ,  Xing Wei ,  Xinhong Cheng ,  Jing Chen ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L27/12 ,  H01L21/283

CPC分类号： H01L21/84 ,  H01L27/0255 ,  H01L27/1203

摘要： The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.

摘要翻译： 本发明公开了一种SOI CMOS电路中的ESD保护结构。 ESD保护结构包括各种纵向（垂直）PN结结构，其具有用于电流的显着扩大的接合面积。 所得到的装置实现了增加的大电流释放能力。 还公开了制造ESD保护纵向PN结的品种的工艺。 所公开的制造工艺与当前SOI技术的兼容性降低了实施成本并提高了集成度。

公开(公告)号：US20120021571A1

公开(公告)日：2012-01-26

申请号：US12937258

申请日：2010-07-14

申请人： Jing Chen ,  Xiaolu Huang ,  Jiexin Luo ,  Qingqing Wu ,  Xi Wang

发明人： Jing Chen ,  Xiaolu Huang ,  Jiexin Luo ,  Qingqing Wu ,  Xi Wang

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/66545 ,  H01L29/78615

摘要： The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process.

摘要翻译： 本发明公开了一种通过大的倾斜离子注入降低SOI MOS器件的浮体效应的方法，包括以下步骤：（a）将倾斜方向的离子注入到具有形成高掺杂P区的掩埋绝缘层的NMOS中 NMOS的源极区域和掩埋绝缘层之上，其中NMOS的纵向线与倾斜方向之间的角度为15至45度。 通过这种方法，源区下的高掺杂P区和高掺杂N区形成隧道结，以减少浮体效应。 此外，芯片面积不会增加，制造工艺简单，方法与常规CMOS工艺兼容。

公开(公告)号：US20120012931A1

公开(公告)日：2012-01-19

申请号：US13132879

申请日：2010-09-07

申请人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xiaolu Huang ,  Xi Wang

发明人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xiaolu Huang ,  Xi Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78615 ,  H01L29/458 ,  H01L29/78621

摘要： The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology.

摘要翻译： 本发明公开了一种具有BTS结构的SOI MOS器件及其制造方法。 SOI MOS器件的源极区域包括：两个重掺杂N型区域，形成在两个重掺杂N型区域之间的重掺杂P型区域，在重掺杂N型区域上形成的硅化物， 掺杂P型区域和与硅化物接触的浅N型区域; 在重掺杂的P型区域和其上的硅化物之间形成欧姆接触以释放积聚在SOI MOS器件的体区中的空穴，并且消除其浮体效应而不增加芯片面积，并且还克服了诸如降低有效性 现有技术的BTS结构中的设备的信道宽度。 该制造方法包括以下步骤：通过离子注入形成重掺杂的P型区，在源区上方形成金属层，并通过金属层与Si之间的Si之间的热处理形成硅化物。 本发明中的器件可以通过简化的制造工艺制造，与传统CMOS技术具有很好的兼容性。

公开(公告)号：US20110291191A1

公开(公告)日：2011-12-01

申请号：US12937360

申请日：2010-07-14

申请人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xiaolu Huang ,  Xi Wang

发明人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xiaolu Huang ,  Xi Wang

IPC分类号： H01L29/772

CPC分类号： H01L29/78612 ,  H01L21/266 ,  H01L29/1087 ,  H01L29/66772 ,  H01L29/78624

摘要： The present invention discloses a MOS structure with suppressed floating body effect including a substrate, a buried insulation layer provided on the substrate, and an active area provided on the buried insulation layer comprising a body region, a first conductive type source region and a first conductive type drain region provided on both sides of the body region respectively and a gate region provide on top of the body region, wherein the active area further comprises a highly doped second conductive type region between the first conductive type source region and the buried insulation layer. For manufacturing this structure, implant ions into a first conductive type source region via a mask having an opening thereon forming a highly doped second conductive type region under the first conductive type source region and above the buried insulation layer. The present invention will not increase chip area and is compatible with conventional CMOS process.

摘要翻译： 本发明公开了一种具有抑制的浮体效应的MOS结构，包括基板，设置在基板上的掩埋绝缘层，以及设置在掩埋绝缘层上的有源区，包括主体区，第一导电型源极区和第一导电 型漏极区域分别设置在主体区域的两侧，并且栅极区域提供在主体区域的顶部，其中有源区域还包括在第一导电型源极区域和掩埋绝缘层之间的高度掺杂的第二导电类型区域。 为了制造该结构，通过其上具有开口的掩模将离子注入到第一导电类型源区中，形成在第一导电类型源极区之下和掩埋绝缘层之上的高度掺杂的第二导电类型区。 本发明不会增加芯片面积并且与常规CMOS工艺兼容。

公开(公告)号：US20110254058A1

公开(公告)日：2011-10-20

申请号：US12810578

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang

发明人： Deyuan Xiao ,  Xi Wang

IPC分类号： H01L27/092 ,  H01L29/04

CPC分类号： H01L27/1211 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/42392 ,  H01L29/78696

摘要： A GAA (Gate-All-Around) CMOSFET device includes a semiconductor substrate, a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The surfaces of the first channel and the second channel are substantially surrounded by the gate region. A buried insulation layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the semiconductor substrate to isolate them from one another. The structure is simple, compact and highly integrated, has high carrier mobility, and avoids polysilicon gate depletion and short channel effect.

摘要翻译： GAA（Gate-All-Around）CMOSFET器件包括半导体衬底，具有第一沟道的PMOS区，具有第二沟道的NMOS区和栅极区。 第一通道和第二通道的表面基本上被栅极区域包围。 掩埋绝缘层设置在PMOS区域和NMOS区域之间以及PMOS或NMOS区域与半导体衬底之间以将它们彼此隔离。 结构简单，紧凑，高度集成，具有高载流子迁移率，避免了多晶硅栅极耗尽和短沟道效应。

公开(公告)号：US20110254013A1

公开(公告)日：2011-10-20

申请号：US12810574

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhong Ying Xue

IPC分类号： H01L27/092

CPC分类号： H01L29/78696 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/42392

摘要： A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.

摘要翻译： 混合取向累积模式GAA（Gate-All-Around）CMOSFET包括具有第一通道的PMOS区域，具有第二通道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由p型Si（110）和n型Si（100）形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 根据本发明的装置结构相当简单，紧凑且高度集成。 在积累模式中，电流流过整个跑道状通道。 所公开的装置导致高载流子迁移率。 同时防止多晶硅栅极耗尽和短沟道效应，并且阈值电压增加。