公开(公告)号：US20130228847A1

公开(公告)日：2013-09-05

申请号：US13850868

申请日：2013-03-26

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L29/788

CPC分类号： H01L29/788 ,  H01L29/66757 ,  H01L29/66825 ,  H01L29/7881

摘要： A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface and a floating gate on the P− polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P+ polysilicon layer overlying the upper oxide block layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.

摘要翻译： 提供一种具有薄膜晶体管（TFT）浮动栅极存储单元结构的器件。 该器件包括衬底，衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域。 介电层与第一表面相关联。 所述一个或多个源区或漏区中的每一个包括在第一导电层上的扩散阻挡层上的N +多晶硅层。 N +多晶硅层具有与第一表面基本共面的第二表面。 另外，该器件包括覆盖共面表面的P-多晶硅层和P-多晶硅层上的浮置栅极。 浮栅是由底部氧化物隧道层和上部氧化物阻挡层夹在中间的低压CVD沉积硅层。 此外，该器件包括至少一个由覆盖在上氧化物块层上的P +多晶硅层制成的控制栅极。 提供了制造相同存储单元结构的方法，并且可以重复三维地集成结构。

公开(公告)号：US08481348B2

公开(公告)日：2013-07-09

申请号：US13176632

申请日：2011-07-05

申请人： Fumitake Mieno ,  Youfeng He

发明人： Fumitake Mieno ,  Youfeng He

IPC分类号： H01L21/00

CPC分类号： H01L45/1213 ,  H01L27/15 ,  H01L27/24 ,  H01L45/06

摘要： The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate. The N-type conductive region containing SiC reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.

摘要翻译： 本发明提供一种相变存储器和形成相变存储器的方法。 相变存储器包括存储区域和外围电路区域。 外围电路区域具有周边基板，外围基板中的多个外围浅沟槽隔离（STI）单元，以及周边基板上的周边基板之间和周边STI单元之间的至少一个MOS晶体管。 存储区域具有存储基板，存储基板上的N型离子掩埋层，N型离子掩埋层上的多个垂直LED，垂直LED之间的多个存储浅沟槽隔离（STI）单元， 以及在垂直LED上和存储STI单元之间的多个相变层。 存储STI单元的厚度基本上等于垂直LED的厚度。 外围STI单元的厚度基本上等于存储STI单元的厚度。 N型导电区域包含SiC。 P型导电区域的顶部与外围基板的顶部齐平。 含有SiC的N型导电区域通过垂直LED降低漏极电流并提高垂直LED的电流效率。 外围电路区域可以正常工作，而不会对相变存储器的性能产生不利影响。

公开(公告)号：US20130020655A1

公开(公告)日：2013-01-24

申请号：US13351139

申请日：2012-01-16

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7781

摘要： The present invention relates to a semiconductor device and its manufacturing method. The semiconductor device comprises: a gate structure located on a substrate, Ge-containing semiconductor layers located on the opposite sides of the gate structure, a doped semiconductor layer epitaxially grown between the Ge-containing semiconductor layers, the bottom surfaces of the Ge-containing semiconductor layers located on the same horizontal plane as that of the epitaxial semiconductor layer. The epitaxial semiconductor layer is used as a channel region, and the Ge-containing semiconductor layers are used as source/drain extension regions.

摘要翻译： 本发明涉及一种半导体器件及其制造方法。 半导体器件包括：位于衬底上的栅极结构，位于栅极结构的相对侧上的含锗半导体层，外延生长在含锗半导体层之间的掺杂半导体层，含Ge的半导体层的底表面 位于与外延半导体层相同的水平面上的半导体层。 使用外延半导体层作为沟道区，将含Ge半导体层用作源/漏延伸区。

公开(公告)号：US08273639B2

公开(公告)日：2012-09-25

申请号：US12132459

申请日：2008-06-03

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

IPC分类号： H01L21/20

CPC分类号： C23C16/04 ,  C23C16/45527 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/31616 ,  H01L21/3185

摘要： Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding an inert purge gas to the semiconductor substrate within the chamber to remove the first precursor gas which has not formed the first discrete monolayer on the semiconductor substrate; feeding a second precursor gas to the chamber to react with the first precursor gas which has formed the first discrete monolayer, forming a discrete atomic size islands; and feeding an inert purge gas to the semiconductor substrate within the chamber to remove the second precursor gas which has not reacted with the first precursor gas and byproducts produced by the reaction between the first and the second precursor gases.

摘要翻译： 公开了原子层沉积方法和包括原子层的半导体器件，包括以下步骤：将半导体衬底放置在原子层沉积室中; 将第一前体气体供给到腔室内的半导体衬底，以在半导体衬底上形成第一离散单层; 向腔室内的半导体衬底供给惰性清洗气体以去除在半导体衬底上未形成第一离散单层的第一前体气体; 将第二前体气体供给到所述室中以与形成所述第一离散单层的所述第一前体气体反应，形成离散的原子尺寸岛; 以及将惰性吹扫气体供给到室内的半导体衬底以除去未与第一前体气体反应的第二前体气体和由第一和第二前体气体之间的反应产生的副产物。

公开(公告)号：US20120168853A1

公开(公告)日：2012-07-05

申请号：US13419943

申请日：2012-03-14

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno ,  Seanfuxiong Zhang

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno ,  Seanfuxiong Zhang

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  C23C16/45529 ,  H01L29/1608 ,  H01L29/40117 ,  H01L29/42348

摘要： A semiconductor non-volatile memory (NVM) device, comprising: a semiconductor substrate; a three-layer stack structure of medium layer-charge trapping layer-medium layer disposed on the semiconductor substrate; a gate disposed above the three-layer stack structure; a source and a drain disposed in the semiconductor substrate at either side of the three-layer stack structure; wherein the charge trapping layer is a dielectric layer containing one or more discrete compound clusters formed by atomic layer deposition (ALD) method.

摘要翻译： 一种半导体非易失性存储器（NVM）器件，包括：半导体衬底; 设置在半导体衬底上的中层电荷俘获层 - 介质层的三层堆叠结构; 设置在三层堆叠结构上方的栅极; 在三层堆叠结构的任一侧设置在半导体衬底中的源极和漏极; 其中电荷捕获层是包含通过原子层沉积（ALD）方法形成的一个或多个离散化合物簇的电介质层。

公开(公告)号：US07569487B2

公开(公告)日：2009-08-04

申请号：US11536472

申请日：2006-09-28

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L21/44

CPC分类号： C23C16/0227

摘要： A method for forming atomic layer deposition. The method includes placing a semiconductor substrate (e.g., wafer, LCD panel) including an upper surface in a chamber. The upper surface includes one or more carbon bearing species and a native oxide layer. The method includes introducing an oxidizing species into the chamber. The method includes treating the upper surface of the semiconductor substrate to remove the one or more carbon bearing species and form a particle film of silicon dioxide overlying the upper surface. The method includes introducing an inert gas into the chamber to purge the chamber of the oxidizing species and other species associated with the one or more carbon bearing species. A reducing species is introduced into the chamber to strip the particle film of silicon dioxide to create a substantially clean surface treated with hydrogen bearing species. The method includes performing another process (e.g., atomic layer deposition) on the substantially clean surface while the substrate is maintained in a vacuum environment. The substantially clean surface is substantially free from native oxide and carbon bearing particles.

摘要翻译： 一种形成原子层沉积的方法。 该方法包括将包括上表面的半导体衬底（例如，晶片，LCD面板）放置在腔室中。 上表面包括一个或多个碳承载物质和天然氧化物层。 该方法包括将氧化物质引入室中。 该方法包括处理半导体衬底的上表面以除去一种或多种含碳物质并形成覆盖在上表面上的二氧化硅的颗粒膜。 该方法包括将惰性气体引入室中以净化氧化物质的室和与一种或多种含碳物质相关联的其它物质。 将还原物质引入室中以剥离二氧化硅的颗粒膜以产生用含氢物质处理的基本上清洁的表面。 该方法包括在基板保持在真空环境中时在基本上清洁的表面上执行另一工艺（例如，原子层沉积）。 基本上干净的表面基本上不含有自然氧化物和碳的颗粒。

公开(公告)号：US20080135906A1

公开(公告)日：2008-06-12

申请号：US11549118

申请日：2006-10-13

申请人： Roger Lee ,  Guoqing Chen ,  Fumitake Mieno

发明人： Roger Lee ,  Guoqing Chen ,  Fumitake Mieno

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L28/84 ,  H01L27/10852

摘要： A dynamic random access memory device including a capacitor structure, e.g., trench, stack. The device includes a substrate (e.g., silicon, silicon on insulator, epitaxial silicon) having a surface region. The device includes an interlayer dielectric region overlying the surface region. In a preferred embodiment, the interlayer dielectric region has an upper surface and a lower surface. The device has a container structure within a portion of the interlayer dielectric region. The container structure extends from the upper surface to the lower surface. The container structure has a first width at the upper surface and a second width at the lower surface. The container structure has an inner region extending from the upper surface to the lower surface. In a specific embodiment, the container structure has a higher dopant concentration within a portion of the inner region within a vicinity of the lower surface and on a portion of the inner region near the vicinity of the lower surface. The device also has a doped polysilicon layer overlying the inner region of the trench structure. The device has a first hemispherical grained silicon material having a first grain dimension near the vicinity of the lower surface and a second hemispherical grained silicon material having a second grain dimension near a vicinity of the upper surface of the container structure. In a preferred embodiment, the first grain dimension has an average size of no greater than about ½ of an average size of the second grain dimension to prevent any bridging of any portions of the hemispherical grained silicon material within the vicinity of the lower surface.

摘要翻译： 包括电容器结构的动态随机存取存储器件，例如沟槽，堆叠。 该器件包括具有表面区域的衬底（例如，硅，绝缘体上的硅，外延硅）。 该器件包括覆盖表面区域的层间电介质区域。 在优选实施例中，层间电介质区域具有上表面和下表面。 该器件在层间电介质区域的一部分内具有容器结构。 容器结构从上表面延伸到下表面。 容器结构在上表面具有第一宽度，在下表面具有第二宽度。 容器结构具有从上表面延伸到下表面的内部区域。 在具体实施方案中，容器结构在下表面附近的内部区域的一部分内部和靠近下表面的内部区域的一部分上具有较高的掺杂剂浓度。 器件还具有覆盖在沟槽结构的内部区域上的掺杂多晶硅层。 该器件具有第一半球形晶体硅材料，其具有靠近下表面附近的第一晶粒尺寸和在容器结构的上表面附近具有第二晶粒尺寸的第二半球形晶粒硅材料。 在优选实施例中，第一晶粒尺寸具有不大于第二晶粒尺寸平均尺寸的约1/2的平均尺寸，以防止半球形晶粒硅材料的任何部分在下表面附近的任何桥接。

公开(公告)号：US5881876A

公开(公告)日：1999-03-16

申请号：US725331

申请日：1996-10-01

申请人： Masahiro Nonomura ,  Akihiko Morita ,  Naoko Onodera ,  Fumitake Mieno

发明人： Masahiro Nonomura ,  Akihiko Morita ,  Naoko Onodera ,  Fumitake Mieno

IPC分类号： B08B1/00 ,  G11B23/50 ,  H01L21/00 ,  H01L21/304 ,  A47L13/17

CPC分类号： H01L21/67046 ,  G11B23/505 ,  Y10T428/1376

摘要： A method and apparatus for storing a brush body, made of a hydrophilic sponge-like porous material in a readily usable condition employs a substrate cleaning brush stored in a vessel, which vessel is filled with liquid such that the brush body is submerged in the liquid.

摘要翻译： 一种容易使用的用于存储由亲水性海绵状多孔质材料制成的刷体的方法和装置，采用容纳在容器中的基材清洗刷，该容器充满液体，使得刷体浸没在液体中 。

公开(公告)号：US5589410A

公开(公告)日：1996-12-31

申请号：US279205

申请日：1994-07-22

申请人： Noriaki Sato ,  Fumitake Mieno

发明人： Noriaki Sato ,  Fumitake Mieno

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/265

CPC分类号： H01L29/66651 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1033 ,  H01L29/1083

摘要： A structure and its fabrication method of an integrated semiconductor device including circuit elements such as MOSFETs. A well is formed in the semiconductor substrate within windows of a field oxide layer. A lightly-doped semiconductor layer is selectively formed on the exposed surface of the well. A channel region and a pair of source and drain regions of a MOSFET are formed in the lightly-doped semiconductor layer. The highly-doped buried semiconductor layer of the same conductivity type as that of the lightly-doped semiconductor layer is formed under the channel region in the lightly-doped semiconductor layer. The structural features and fabrication method provides a great degree of freedom in designing a MOSFET having a further shorter-channel length without deteriorating its drivability and punch-through breakdown voltage.

摘要翻译： 包括诸如MOSFET的电路元件的集成半导体器件的结构及其制造方法。 在场氧化物层的窗口内的半导体衬底中形成阱。 在井的暴露表面上选择性地形成轻掺杂半导体层。 MOSFET的沟道区域和一对源极和漏极区域形成在轻掺杂半导体层中。 与轻掺杂半导体层相同的导电类型的高掺杂掩模半导体层形成在轻掺杂半导体层的沟道区的下方。 结构特征和制造方法在设计具有更短通道长度的MOSFET的同时提供了很大的自由度，而不会降低其驱动能力和穿通击穿电压。

公开(公告)号：US5362981A

公开(公告)日：1994-11-08

申请号：US699

申请日：1993-01-05

申请人： Noriaki Sato ,  Fumitake Mieno

发明人： Noriaki Sato ,  Fumitake Mieno

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L27/02 ,  H01L27/04 ,  H01L27/12

CPC分类号： H01L29/66651 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1033 ,  H01L29/1083

摘要： A structure and its fabrication method of an integrated semiconductor device including circuit elements such as MOSFETs. A well is formed in the semiconductor substrate within windows of a field oxide layer. A lightly-doped semiconductor layer is selectively formed on the exposed surface of the well. A channel region and a pair of source and drain regions of a MOSFET are formed in the lightly-doped semiconductor layer. The highly-doped buried semiconductor layer of the same conductivity type as that of the lightly-doped semiconductor layer is formed under the channel region in the lightly-doped semiconductor layer. The structural features and fabrication method provides a great degree of freedom in designing a MOSFET having a further shorter-channel length without deteriorating its drivability and punch-through breakdown voltage.

摘要翻译： 包括诸如MOSFET的电路元件的集成半导体器件的结构及其制造方法。 在场氧化物层的窗口内的半导体衬底中形成阱。 在井的暴露表面上选择性地形成轻掺杂半导体层。 MOSFET的沟道区域和一对源极和漏极区域形成在轻掺杂半导体层中。 与轻掺杂半导体层相同的导电类型的高掺杂掩模半导体层形成在轻掺杂半导体层的沟道区的下方。 结构特征和制造方法在设计具有更短通道长度的MOSFET的同时提供了很大的自由度，而不会降低其驱动能力和穿通击穿电压。