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公开(公告)号：US07447831B2
公开(公告)日：2008-11-04
申请号：US11383989
申请日：2006-05-18
IPC分类号： G06F13/14
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.
摘要翻译： 公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。 出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。 第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。
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52.发明授权System, method and storage medium for providing a service interface to a memory system 有权用于向存储器系统提供服务接口的系统，方法和存储介质公开(公告)号：US07441060B2
公开(公告)日：2008-10-21
申请号：US10977921
申请日：2004-10-29
IPC分类号： G06F13/00
CPC分类号： G06F13/4243
摘要： A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module.
摘要翻译： 用于向存储器系统提供服务接口的级联互连系统。 级联互联系统包括主服务接口模块，业务接口总线以及一个或多个从业务接口模块。 主服务接口模块和从接口模块通过业务接口总线级联互联。 每个从业务接口模块与相应的存储器模块通信，用于向存储器模块提供服务。
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公开(公告)号：US20080183903A1
公开(公告)日：2008-07-31
申请号：US11668088
申请日：2007-01-29
申请人： Dustin J. VanStee , Kevin C. Gower
发明人： Dustin J. VanStee , Kevin C. Gower
IPC分类号： G06F3/00
CPC分类号： G06F13/161
摘要： Systems and methods for providing dynamic memory pre-fetch. Embodiments include a hub device including an input command stream interface and an adaptive pre-fetch logical unit (APLU). The input command stream interface detects commands from a memory controller directed to one or more memory devices that are connected to the hub device. The APLU independently analyzes the commands to determine access patterns to the memory devices. The APLU also dynamically selects between enabling a pre-fetch function and disabling the pre-fetch function for the memory devices based on the results of the analysis.
摘要翻译： 提供动态内存预取的系统和方法。 实施例包括包括输入命令流接口和自适应预取逻辑单元（APLU）的集线器设备。 输入命令流接口检测来自指向连接到集线器设备的一个或多个存储器设备的存储器控制器的命令。 APLU独立分析命令以确定存储器件的访问模式。 APLU还可以根据分析结果动态选择启用预取功能和禁用存储设备的预取功能。
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54.发明申请SYSTEM, METHOD AND STORAGE MEDIUM FOR A MEMORY SUBSYSTEM COMMAND INTERFACE 失效用于记忆子系统命令界面的系统，方法和存储介质公开(公告)号：US20080177929A1
公开(公告)日：2008-07-24
申请号：US12059164
申请日：2008-03-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/04
CPC分类号： G06F13/1684
摘要： A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of commands. The memory controller and the memory module are interconnected by a packetized multi-transfer interface via the memory bus and the frame is transmitted to the memory modules via the memory bus.
摘要翻译： 一种用于实现存储器子系统命令接口的系统，该系统包括包括一个或多个存储器模块，存储器控制器和存储器总线的级联互连系统。 存储器控制器生成包括多个命令的数据帧。 存储器控制器和存储器模块通过存储器总线通过分组化的多传输接口互连，并且帧经由存储器总线传送到存储器模块。
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公开(公告)号：US20070297397A1
公开(公告)日：2007-12-27
申请号：US11426047
申请日：2006-06-23
IPC分类号： H04L12/50
CPC分类号： G06F13/1684 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module, where memory module includes a memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, with the high speed memory bus connected to the memory hub device by a negligible electrical stub.
摘要翻译： 公开了包括存储器控制器的存储器系统; 一个内存总线终端; 连接存储器控制器，存储器总线终端器和至少一个存储器模块的高速存储器总线，其中存储器模块包括存储器集线器设备，由存储器集线器设备服务的高速随机存取存储器，两个总线信号端口和 在存储器模块上制造的高速存储器总线的一段，以便将总线信号端口和存储器集线器设备互连，高速存储器总线通过可忽略的电接头连接到存储器集线器装置。
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56.发明授权System, method and storage medium for a memory subsystem command interface 失效用于内存子系统命令界面的系统，方法和存储介质公开(公告)号：US07299313B2
公开(公告)日：2007-11-20
申请号：US10977793
申请日：2004-10-29
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F13/1684
摘要： A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of commands. The memory controller and the memory module are interconnected by a packetized multi-transfer interface via the memory bus and the frame is transmitted to the memory modules via the memory bus.
摘要翻译： 一种用于实现存储器子系统命令接口的系统，该系统包括包括一个或多个存储器模块，存储器控制器和存储器总线的级联互连系统。 存储器控制器生成包括多个命令的数据帧。 存储器控制器和存储器模块通过存储器总线通过分组化的多传输接口互连，并且帧经由存储器总线传送到存储器模块。
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公开(公告)号：US07282790B2
公开(公告)日：2007-10-16
申请号：US11146495
申请日：2005-06-06
CPC分类号： G11C5/04 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H05K1/181 , H05K2201/10159 , H01L2224/0401
摘要： A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.
摘要翻译： 一种平面存储器模块（PAMM）装置，包括大致平面的卡，包括第一侧和第二侧，所述第一侧具有多个耦合，所述第二侧具有多个连接器，多个存储器件耦合到所述卡经由 所述多个联接器的第一部分以及经由所述多个联接器的第二部分耦合到所述卡的至少一个毂芯片。 多个联接器中的每一个连接到多个连接器中的相关联的一个。
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58.发明授权Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability 失效内存自检引擎装置和方法，具有故障触发和每种负载能力的多种模式公开(公告)号：US07181659B2
公开(公告)日：2007-02-20
申请号：US11055195
申请日：2005-02-10
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C11/401
摘要： A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.
摘要翻译： 用于测试动态随机存取存储器（DRAM）阵列的存储器内置自检（MBIST）装置和方法，所述DRAM阵列与包括接口逻辑和主线芯片逻辑的存储器接口装置通信。 MBIST装置包括有限状态机，其包括用于递增待测数据和地址的命令发生器和逻辑，以及与有限状态机通信的命令调度器。 命令调度器包括用于动态地利用DRAM时序参数将命令间隔到存储器的资源分配逻辑。 MBIST设备还包括存储MBIST测试的分测验的测试存储器。 每个分测验提供完整的配置地址范围。 MBIST装置还包括与测试存储器和有限状态机通信的子测试指针。 有限状态机通过子测验指针实现每个子测验的子测序。
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59.发明授权DIGITAL-TO-ANALOG CONVERTER (DAC) FOR DYNAMIC ADJUSTMENT OF OFF-CHIP DRIVER PULL-UP AND PULL DOWN IMPEDANCE BY PROVIDING A VARIABLE REFERENCE VOLTAGE TO HIGH FREQUENCY RECEIVER AND DRIVER CIRCUITS FOR COMMERCIAL MEMORY 失效数字模拟转换器（DAC）用于通过向高频接收器和商用存储器的驱动电路提供可变参考电压来动态调整脱离芯片驱动器的上拉和下拉电阻公开(公告)号：US06515917B2
公开(公告)日：2003-02-04
申请号：US09829628
申请日：2001-04-10
申请人： Kirk D. Lamb , Kevin C. Gower , Edward N. Cohen
发明人： Kirk D. Lamb , Kevin C. Gower , Edward N. Cohen
IPC分类号： G11C700
CPC分类号： G11C5/147 , G11C5/04 , G11C5/143 , G11C7/04 , G11C7/1051 , G11C7/1069 , G11C7/1072 , G11C7/20 , G11C11/4072 , G11C11/4093 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50008 , G11C2029/0407 , G11C2029/0409
摘要： A memory subsystem package has a memory controller interface ASIC (application specific integrated circuit) and a plurality of Memory modules. The ASIC has a bi-directional serial protocol i2C communication bus to off chip drivers for monitoring temperature and for adjusting the environment surrounding the package by controlling fans using fan switches and variable voltage controls. In addition there is provided an Alternating Current Built in Self Test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test for that ASIC enabling writing of pseudo-random patterns to memory, reading them back and comparing the expected results at hardware speeds. Vref can be made to vary across its allowable range during AC self test to provide improved coverage. The system monitors Vddq during normal system operation using an ADC. The system varies Vref as a function of Vddq, using a combination of a DAC and ADC. The system varies Vref as a function of Vddq, such that Vref=1/m*Vddq+OFFSET, where m can be 1, 2, 4, or 8, and where OFFSET can be positive or negative ranging from 1/n * Vddq to n−1/n*Vddq, where n is the voltage granularity of the DAC.
摘要翻译： 存储器子系统包具有存储器控制器接口ASIC（专用集成电路）和多个存储器模块。 ASIC具有双向串行协议i2C通信总线到芯片外驱动器，用于监控温度，并通过使用风扇开关和可变电压控制控制风扇来调节封装周围的环境。 此外，还提供了具有可变数据接收器电压参考的内置自测（AC BIST）的交流电，用于为该ASIC执行高速AC存储器子系统自检，使得能够将伪随机模式写入存储器，读取它们， 在硬件速度下比较预期结果。 在AC自检期间，可以使Vref在其允许范围内变化，以提供更好的覆盖。 系统使用ADC在系统正常运行期间监视Vddq。 该系统使用DAC和ADC的组合，将Vdd变为Vddq的函数。 该系统将Vref作为Vddq的函数，使得Vref = 1 / m * Vddq + OFFSET，其中m可以是1,2,4或8，并且其中OFFSET可以是正或负范围从1 / n * Vddq 到n-1 / n * Vddq，其中n是DAC的电压粒度。
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60.发明授权Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device 失效通过向DRAM设备发出电源开/关命令，对缓冲DIMM上的备用DRAM进行电源管理公开(公告)号：US08639874B2
公开(公告)日：2014-01-28
申请号：US12341515
申请日：2008-12-22
IPC分类号： G06F12/06
CPC分类号： G11C5/06 , G11C5/04 , G11C5/14 , G11C11/4074
摘要： A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.
摘要翻译： 一种具有一个或多个具有内部存储器阵列的半导体存储器件的计算机存储器，所述内部存储器阵列包括排列成行和列的矩阵的多个半导体动态随机存取存储器（DRAM）单元，并被提供为这种存储器的存储器模块等级 在基板上的一个或多个所述半导体存储器件的DIMM上布置的阵列中的器件，其可以经由存储器件数据接口耦合到作为存储器子系统的存储器系统，每个所述存储器件具有低功率闭合 - 可以使用公共存储器数据接口激活。 通过数据接口对DRAM的功率的控制问题DRAM功率控制命令的两个命令解码，功率状态程序信号和功率状态复位信号作为功率状态控制命令来控制所述DRAM的功率状态， 并激活用于将存储器单元作为正常的有源或备用设备读/写。
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