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公开(公告)号：US20090119466A1
公开(公告)日：2009-05-07
申请号：US12352990
申请日：2009-01-13
申请人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
发明人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06F11/3419 , G06F11/3476 , G06F11/349 , G06F2201/86 , G06F2201/88 , Y02D10/14 , Y02D10/34
摘要： Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.
摘要翻译： 用于在存储器系统中提供性能监视的系统。 存储器系统包括存储器控制器，多个存储器件，存储器总线和存储器集线器设备。 存储器控制器接收和响应存储器访问请求。 存储器总线与存储器控制器通信。 存储器集线器设备与存储器总线通信。 存储器集线器设备包括用于经由存储器总线在存储器集线器设备和存储器控制器之间传送地址，控制和数据信息中的一个或多个的存储器接口。 存储器集线器设备还包括用于与存储器件通信的存储器设备接口。 存储器集线器设备还包括性能监视器，用于在系统操作期间在定义的间隔上监视和报告存储器总线利用率，存储器件利用率和性能特性中的一个或多个。
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2.发明授权公开(公告)号：US07493439B2
公开(公告)日：2009-02-17
申请号：US11461567
申请日：2006-08-01
申请人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
发明人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
CPC分类号： G06F13/1668 , G06F11/3419 , G06F11/3476 , G06F11/349 , G06F2201/86 , G06F2201/88 , Y02D10/14 , Y02D10/34
摘要： Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.
摘要翻译： 在存储系统中提供性能监控的系统和方法。 实施例包括用于存储和检索用于处理系统的数据的存储器系统。 存储器系统包括存储器控制器，多个存储器件，存储器总线和存储器集线器设备。 存储器控制器接收和响应存储器访问请求。 存储器总线与存储器控制器通信。 存储器集线器设备与存储器总线通信。 存储器集线器设备包括用于经由存储器总线在存储器集线器设备和存储器控制器之间传送地址，控制和数据信息中的一个或多个的存储器接口。 存储器集线器设备还包括用于与存储器件通信的存储器设备接口。 存储器集线器设备还包括性能监视器，用于在系统操作期间在定义的间隔上监视和报告存储器总线利用率，存储器件利用率和性能特性中的一个或多个。
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公开(公告)号：US20080183977A1
公开(公告)日：2008-07-31
申请号：US11668093
申请日：2007-01-29
申请人： Kevin C. Gower , Dustin J. VanStee
发明人： Kevin C. Gower , Dustin J. VanStee
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G06F12/0215 , G06F13/161 , G06F13/1684
摘要： Systems and methods for providing a dynamic memory buffer bank policy. Embodiments include a hub device for selecting a bank page policy. The hub device includes an input command stream interface and a bank page policy module. The input command stream interface detects commands from a memory controller that are directed to one or more memory devices that are connected to the hub device. The bank page policy module independently analyzes the commands to determine access patterns to the memory devices and for dynamically selecting between an open bank page policy and a closed bank page policy for the memory devices based on the analysis.
摘要翻译： 提供动态内存缓冲区银行策略的系统和方法。 实施例包括用于选择银行页面策略的集线器设备。 集线器设备包括输入命令流接口和银行页策略模块。 输入命令流接口检测来自存储器控制器的命令，其被定向到连接到集线器设备的一个或多个存储器设备。 银行页面策略模块独立地分析用于确定对存储器设备的访问模式的命令，并且基于分析来动态地在存储设备的开放银行页面策略和封闭的银行页面策略之间进行选择。
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4.发明授权公开(公告)号：US07669086B2
公开(公告)日：2010-02-23
申请号：US11461933
申请日：2006-08-02
IPC分类号： G06F11/00
CPC分类号： G06F13/4239 , G06F9/52
摘要： Systems and methods for providing collision detection in a memory system including a memory system for storing and retrieving data for a processing system. The memory system includes resource scheduling conflict logic for monitoring one or more memory resources for detecting resource scheduling conflicts. The memory system also includes error reporting logic for generating an error signal in response to detecting a resource scheduling conflict at one or more of the memory resources.
摘要翻译： 用于在包括用于存储和检索用于处理系统的数据的存储器系统的存储器系统中提供冲突检测的系统和方法。 存储器系统包括用于监视用于检测资源调度冲突的一个或多个存储器资源的资源调度冲突逻辑。 存储器系统还包括用于响应于检测到一个或多个存储器资源上的资源调度冲突而产生错误信号的错误报告逻辑。
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公开(公告)号：US20080183903A1
公开(公告)日：2008-07-31
申请号：US11668088
申请日：2007-01-29
申请人： Dustin J. VanStee , Kevin C. Gower
发明人： Dustin J. VanStee , Kevin C. Gower
IPC分类号： G06F3/00
CPC分类号： G06F13/161
摘要： Systems and methods for providing dynamic memory pre-fetch. Embodiments include a hub device including an input command stream interface and an adaptive pre-fetch logical unit (APLU). The input command stream interface detects commands from a memory controller directed to one or more memory devices that are connected to the hub device. The APLU independently analyzes the commands to determine access patterns to the memory devices. The APLU also dynamically selects between enabling a pre-fetch function and disabling the pre-fetch function for the memory devices based on the results of the analysis.
摘要翻译： 提供动态内存预取的系统和方法。 实施例包括包括输入命令流接口和自适应预取逻辑单元（APLU）的集线器设备。 输入命令流接口检测来自指向连接到集线器设备的一个或多个存储器设备的存储器控制器的命令。 APLU独立分析命令以确定存储器件的访问模式。 APLU还可以根据分析结果动态选择启用预取功能和禁用存储设备的预取功能。
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6.发明授权Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability 失效内存自检引擎装置和方法，具有故障触发和每种负载能力的多种模式公开(公告)号：US07181659B2
公开(公告)日：2007-02-20
申请号：US11055195
申请日：2005-02-10
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C11/401
摘要： A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.
摘要翻译： 用于测试动态随机存取存储器（DRAM）阵列的存储器内置自检（MBIST）装置和方法，所述DRAM阵列与包括接口逻辑和主线芯片逻辑的存储器接口装置通信。 MBIST装置包括有限状态机，其包括用于递增待测数据和地址的命令发生器和逻辑，以及与有限状态机通信的命令调度器。 命令调度器包括用于动态地利用DRAM时序参数将命令间隔到存储器的资源分配逻辑。 MBIST设备还包括存储MBIST测试的分测验的测试存储器。 每个分测验提供完整的配置地址范围。 MBIST装置还包括与测试存储器和有限状态机通信的子测试指针。 有限状态机通过子测验指针实现每个子测验的子测序。
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7.发明授权System and method for providing a configurable command sequence for a memory interface device 失效为存储器接口设备提供可配置命令序列的系统和方法公开(公告)号：US07979616B2
公开(公告)日：2011-07-12
申请号：US11767118
申请日：2007-06-22
CPC分类号： G06F13/1684
摘要： A system and method for providing a configurable command sequence for a memory interface device (MID). The system includes a MID intended for use in a cascade interconnect system and in communication with one or more memory devices. The MID includes a first connection to a high speed bus operating at a first data rate, a second connection to the high speed bus, an alternate communication means and logic. The first connection to the high speed bus includes receiver circuitry operating at the first data rate. The alternate communication means operates at a second data rate that is slower than the first data rate. The logic facilitates receiving commands via the first connection from the high speed bus operating at the first data rate and using a first command sequence. The logic also facilitates receiving the commands via the alternate communication means using a second command sequence which differs from the first command sequence in the speed in which the commands are transferred. The logic further facilitates processing the commands if the commands are directed to the MID and redriving the commands via the second connection onto the high speed bus.
摘要翻译： 一种用于为存储器接口设备（MID）提供可配置命令序列的系统和方法。 该系统包括MID，其用于级联互连系统并与一个或多个存储器件通信。 MID包括与以第一数据速率操作的高速总线的第一连接，到高速总线的第二连接，备用通信装置和逻辑。 与高速总线的第一连接包括以第一数据速率工作的接收器电路。 备用通信装置以比第一数据速率慢的第二数据速率工作。 该逻辑有助于通过第一连接从第一数据速率的高速总线接收命令并使用第一命令序列。 逻辑还通过使用与命令传送的速度不同的第一命令序列的第二命令序列，便于经由备用通信装置接收命令。 如果命令指向MID并通过第二连接将命令重新转移到高速总线上，则该逻辑进一步有助于处理命令。
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8.发明授权System and method for providing synchronous dynamic random access memory (SDRAM) mode register shadowing in a memory system 失效用于在存储器系统中提供同步动态随机存取存储器（SDRAM）模式寄存器阴影的系统和方法公开(公告)号：US07624225B2
公开(公告)日：2009-11-24
申请号：US11689647
申请日：2007-03-22
IPC分类号： G06F12/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/10 , G11C7/1003
摘要： A system and method for providing SDRAM mode register shadowing in a memory system. A system includes a memory interface device adapted for use in a memory system. The memory interface device includes an interface to one or more ranks of memory devices, and each memory device includes one or more types of mode registers. The memory interface device also includes an interface to a memory bus for receiving commands from a memory controller. The commands include a mode register set command specifying a new mode register setting for one or more ranks of memory devices and a mode register type. The memory interface device further includes a mode register shadow module to capture settings applied to the mode registers. The module includes a shadow register for each type of mode register and a shadow log for each type of mode register. The module also includes mode register shadow logic to detect a mode register set command, to store the new mode register setting in the shadow register corresponding to the specified mode register type, and to set one or more bits in the shadow log corresponding to the specified mode register type to indicate which of the ranks of memory devices have been programmed with the new mode register setting.
摘要翻译： 一种用于在存储器系统中提供SDRAM模式寄存器阴影的系统和方法。 系统包括适于在存储器系统中使用的存储器接口设备。 存储器接口设备包括到一个或多个存储器设备等级的接口，并且每个存储器设备包括一种或多种类型的模式寄存器。 存储器接口设备还包括到存储器总线的接口，用于从存储器控制器接收命令。 这些命令包括指定用于一个或多个存储器件级别的模式寄存器设置的模式寄存器设置命令和模式寄存器类型。 存储器接口设备还包括模式寄存器阴影模块，用于捕获应用于模式寄存器的设置。 该模块包括每种类型的模式寄存器的影子寄存器和每种类型的模式寄存器的影子日志。 该模块还包括模式寄存器阴影逻辑，用于检测模式寄存器设置命令，将新模式寄存器设置存储在与指定模式寄存器类型相对应的影子寄存器中，并设置与指定的对应的影子日志中的一个或多个位 模式寄存器类型，以指示使用新模式寄存器设置来编程存储器件的哪些等级。
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公开(公告)号：US07984222B2
公开(公告)日：2011-07-19
申请号：US12352990
申请日：2009-01-13
申请人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
发明人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
CPC分类号： G06F13/1668 , G06F11/3419 , G06F11/3476 , G06F11/349 , G06F2201/86 , G06F2201/88 , Y02D10/14 , Y02D10/34
摘要： Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.
摘要翻译： 用于在存储器系统中提供性能监视的系统。 存储器系统包括存储器控制器，多个存储器件，存储器总线和存储器集线器设备。 存储器控制器接收和响应存储器访问请求。 存储器总线与存储器控制器通信。 存储器集线器设备与存储器总线通信。 存储器集线器设备包括用于经由存储器总线在存储器集线器设备和存储器控制器之间传送地址，控制和数据信息中的一个或多个的存储器接口。 存储器集线器设备还包括用于与存储器件通信的存储器设备接口。 存储器集线器设备还包括性能监视器，用于在系统操作期间在定义的间隔上监视和报告存储器总线利用率，存储器件利用率和性能特性中的一个或多个。
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10.发明申请SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE COMMAND SEQUENCE FOR A MEMORY INTERFACE DEVICE 失效用于为存储器接口设备提供可配置命令序列的系统和方法公开(公告)号：US20080320191A1
公开(公告)日：2008-12-25
申请号：US11767118
申请日：2007-06-22
IPC分类号： G06F13/00
CPC分类号： G06F13/1684
摘要： A system and method for providing a configurable command sequence for a memory interface device (MID). The system includes a MID intended for use in a cascade interconnect system and in communication with one or more memory devices. The MID includes a first connection to a high speed bus operating at a first data rate, a second connection to the high speed bus, an alternate communication means and logic. The first connection to the high speed bus includes receiver circuitry operating at the first data rate. The alternate communication means operates at a second data rate that is slower than the first data rate. The logic facilitates receiving commands via the first connection from the high speed bus operating at the first data rate and using a first command sequence. The logic also facilitates receiving the commands via the alternate communication means using a second command sequence which differs from the first command sequence in the speed in which the commands are transferred. The logic further facilitates processing the commands if the commands are directed to the MID and redriving the commands via the second connection onto the high speed bus.
摘要翻译： 一种用于为存储器接口设备（MID）提供可配置命令序列的系统和方法。 该系统包括MID，其用于级联互连系统并与一个或多个存储器件通信。 MID包括与以第一数据速率操作的高速总线的第一连接，到高速总线的第二连接，备用通信装置和逻辑。 与高速总线的第一连接包括以第一数据速率工作的接收器电路。 备用通信装置以比第一数据速率慢的第二数据速率工作。 该逻辑有助于通过第一连接从第一数据速率的高速总线接收命令并使用第一命令序列。 逻辑还通过使用与命令传送的速度不同的第一命令序列的第二命令序列，便于经由备用通信装置接收命令。 如果命令指向MID并通过第二连接将命令重新转移到高速总线上，则该逻辑进一步有助于处理命令。
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