公开(公告)号：US06515917B2

公开(公告)日：2003-02-04

申请号：US09829628

申请日：2001-04-10

申请人： Kirk D. Lamb ,  Kevin C. Gower ,  Edward N. Cohen

发明人： Kirk D. Lamb ,  Kevin C. Gower ,  Edward N. Cohen

IPC分类号： G11C700

CPC分类号： G11C5/147 ,  G11C5/04 ,  G11C5/143 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50008 ,  G11C2029/0407 ,  G11C2029/0409

摘要： A memory subsystem package has a memory controller interface ASIC (application specific integrated circuit) and a plurality of Memory modules. The ASIC has a bi-directional serial protocol i2C communication bus to off chip drivers for monitoring temperature and for adjusting the environment surrounding the package by controlling fans using fan switches and variable voltage controls. In addition there is provided an Alternating Current Built in Self Test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test for that ASIC enabling writing of pseudo-random patterns to memory, reading them back and comparing the expected results at hardware speeds. Vref can be made to vary across its allowable range during AC self test to provide improved coverage. The system monitors Vddq during normal system operation using an ADC. The system varies Vref as a function of Vddq, using a combination of a DAC and ADC. The system varies Vref as a function of Vddq, such that Vref=1/m*Vddq+OFFSET, where m can be 1, 2, 4, or 8, and where OFFSET can be positive or negative ranging from 1/n * Vddq to n−1/n*Vddq, where n is the voltage granularity of the DAC.

摘要翻译： 存储器子系统包具有存储器控制器接口ASIC（专用集成电路）和多个存储器模块。 ASIC具有双向串行协议i2C通信总线到芯片外驱动器，用于监控温度，并通过使用风扇开关和可变电压控制控制风扇来调节封装周围的环境。 此外，还提供了具有可变数据接收器电压参考的内置自测（AC BIST）的交流电，用于为该ASIC执行高速AC存储器子系统自检，使得能够将伪随机模式写入存储器，读取它们， 在硬件速度下比较预期结果。 在AC自检期间，可以使Vref在其允许范围内变化，以提供更好的覆盖。 系统使用ADC在系统正常运行期间监视Vddq。 该系统使用DAC和ADC的组合，将Vdd变为Vddq的函数。 该系统将Vref作为Vddq的函数，使得Vref = 1 / m * Vddq + OFFSET，其中m可以是1,2,4或8，并且其中OFFSET可以是正或负范围从1 / n * Vddq 到n-1 / n * Vddq，其中n是DAC的电压粒度。

公开(公告)号：US07624225B2

公开(公告)日：2009-11-24

申请号：US11689647

申请日：2007-03-22

申请人： Kevin C. Gower ,  Thomas J. Griffin ,  Kirk D. Lamb ,  Dustin J. VanStee

发明人： Kevin C. Gower ,  Thomas J. Griffin ,  Kirk D. Lamb ,  Dustin J. VanStee

IPC分类号： G06F12/00

CPC分类号： G11C7/1045 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003

摘要： A system and method for providing SDRAM mode register shadowing in a memory system. A system includes a memory interface device adapted for use in a memory system. The memory interface device includes an interface to one or more ranks of memory devices, and each memory device includes one or more types of mode registers. The memory interface device also includes an interface to a memory bus for receiving commands from a memory controller. The commands include a mode register set command specifying a new mode register setting for one or more ranks of memory devices and a mode register type. The memory interface device further includes a mode register shadow module to capture settings applied to the mode registers. The module includes a shadow register for each type of mode register and a shadow log for each type of mode register. The module also includes mode register shadow logic to detect a mode register set command, to store the new mode register setting in the shadow register corresponding to the specified mode register type, and to set one or more bits in the shadow log corresponding to the specified mode register type to indicate which of the ranks of memory devices have been programmed with the new mode register setting.

摘要翻译： 一种用于在存储器系统中提供SDRAM模式寄存器阴影的系统和方法。 系统包括适于在存储器系统中使用的存储器接口设备。 存储器接口设备包括到一个或多个存储器设备等级的接口，并且每个存储器设备包括一种或多种类型的模式寄存器。 存储器接口设备还包括到存储器总线的接口，用于从存储器控制器接收命令。 这些命令包括指定用于一个或多个存储器件级别的模式寄存器设置的模式寄存器设置命令和模式寄存器类型。 存储器接口设备还包括模式寄存器阴影模块，用于捕获应用于模式寄存器的设置。 该模块包括每种类型的模式寄存器的影子寄存器和每种类型的模式寄存器的影子日志。 该模块还包括模式寄存器阴影逻辑，用于检测模式寄存器设置命令，将新模式寄存器设置存储在与指定模式寄存器类型相对应的影子寄存器中，并设置与指定的对应的影子日志中的一个或多个位 模式寄存器类型，以指示使用新模式寄存器设置来编程存储器件的哪些等级。

公开(公告)号：US07290159B2

公开(公告)日：2007-10-30

申请号：US10853423

申请日：2004-05-25

申请人： Kirk D. Lamb ,  Kevin C. Gower ,  Thomas J. Griffin ,  Steven J. Hnatko ,  Dustin J. VanStee

发明人： Kirk D. Lamb ,  Kevin C. Gower ,  Thomas J. Griffin ,  Steven J. Hnatko ,  Dustin J. VanStee

IPC分类号： G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00

CPC分类号： G06F1/12

摘要： A synchronous input to output protocol translator supporting multiple reference oscillator frequencies and fixed latency data computation and chip crossing circuits enables implementation of a method for delaying osc2 relative to osc1 in a configurable way to provide a constant, minimal Tptcc over a range of refosc frequencies between circuits for data transferred. It requires that the data transferred from a register R1 be sent over multiple wires via configurable delay circuitry for osc2, capture circuitry at the input to R2, and a circuit to transfer a synchronizing signal from a non-delayed clock domain to a delayed clock domain. Relative to osc1, osc2 is a delayed, synchronous clock.

摘要翻译： 支持多个参考振荡器频率和固定等待时间数据计算和芯片交叉电路的输出协议转换器的同步输入使得能够实现一种用于将相对于振荡器1的振荡器2延迟的方法 可配置的方式来在用于传送数据的电路之间的反射率范围内提供恒定的最小Ttcc。 它要求从寄存器R＆lt; 1＆gt; 1传送的数据通过多个导线通过用于osc 2 2的可配置延迟电路发送，在R 2的输入处的捕获电路 / SUB>，以及将同步信号从非延迟时钟域传送到延迟的时钟域的电路。 相对于osc <1> ，osc <2> 是延迟的同步时钟。

公开(公告)号：US06662136B2

公开(公告)日：2003-12-09

申请号：US09829633

申请日：2001-04-10

申请人： Kirk D. Lamb ,  Kevin C. Gower

发明人： Kirk D. Lamb ,  Kevin C. Gower

IPC分类号： G01K108

CPC分类号： H01L23/34 ,  G01K7/42 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  H01L23/467 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A memory subsystem package has a memory controller interface ASIC (application specific integrated circuit) and a plurality of memory modules. The ASIC has a bi-directional serial protocol i2C communication bus to off chip drivers for monitoring temperature and for adjusting the environment surrounding the package by controlling fans using fan switches and variable voltage controls. In addition there is provided an Alternating Current Built in Self Test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test for that ASIC enabling writing of pseudo-random patterns to memory, reading them back and comparing the expected results at hardware speeds. Vref can be made to vary across its allowable range during AC self test to provide improved coverage. The system monitors Vddq during normal system operation using an ADC. The system varies Vref as a function of Vddq, using a combination of a DAC and ADC. The system varies Vref as a function of Vddq, such that Vref=1/m*Vddq+OFFSET, where m can be 1, 2, 4, or 8, and where OFFSET can be positive or negative ranging from 1/n*Vddq to n−1/n*Vddq, where n is the voltage granularity of the DAC.

公开(公告)号：US06757857B2

公开(公告)日：2004-06-29

申请号：US09829630

申请日：2001-04-10

申请人： Kirk D. Lamb ,  Kevin C. Gower ,  Paul W. Coteus

发明人： Kirk D. Lamb ,  Kevin C. Gower ,  Paul W. Coteus

IPC分类号： G01R3128

CPC分类号： G11C29/12 ,  G11C5/147 ,  G11C2207/104

摘要： A memory subsystem package has a memory controller interface ASIC (application specific integrated circuit) and a plurality of memory modules. The ASIC has a bi-directional serial protocol i2C communication bus to off chip drivers for monitoring temperature and for adjusting the environment surrounding the package by controlling fans using fan switches and variable voltage controls. In addition there is provided an Alternating Current Built in Self Test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test for that ASIC enabling writing of pseudo-random patterns to memory, reading them back and comparing the expected results at hardware speeds. Vref can be made to vary across its allowable range during AC self test to provide improved coverage. The system monitors vddq during normal system operation using an ADC. The system varies Vref as a function of Vddq, using a combination of a DAC and ADC. The system varies Vref as a function of Vddq, such that Vref=1/m*Vddq+OFFSET, where m can be 1, 2, 4, or 8, and where OFFSET can be positive or negative ranging from 1/n*Vddq to n−1/n*Vddq, where n is the voltage granularity of the DAC.

摘要翻译： 存储器子系统包具有存储器控制器接口ASIC（专用集成电路）和多个存储器模块。 ASIC具有双向串行协议i2C通信总线到芯片外驱动器，用于监控温度，并通过使用风扇开关和可变电压控制控制风扇来调节封装周围的环境。 此外，还提供了具有可变数据接收器电压参考的内置自测（AC BIST）的交流电，用于为该ASIC执行高速AC存储器子系统自检，使得能够将伪随机模式写入存储器，读取它们， 在硬件速度下比较预期结果。 在AC自检期间，可以使Vref在其允许范围内变化，以提供更好的覆盖。 系统在使用ADC的正常系统操作期间监视vddq。 该系统使用DAC和ADC的组合，将Vdd变为Vddq的函数。 该系统将Vref作为Vddq的函数，使得Vref = 1 / m * Vddq + OFFSET，其中m可以是1,2,4或8，并且其中OFFSET可以是正或负范围从1 / n * Vddq 到n-1 / n * Vddq，其中n是DAC的电压粒度。

公开(公告)号：US06489912B2

公开(公告)日：2002-12-03

申请号：US09829636

申请日：2001-04-10

申请人： Kirk D. Lamb ,  Kevin C. Gower

发明人： Kirk D. Lamb ,  Kevin C. Gower

IPC分类号： H03M112

CPC分类号： G01R31/318385 ,  G01R31/3004 ,  G01R31/3167 ,  G01R31/3187 ,  G11C5/00 ,  G11C5/143 ,  G11C5/147 ,  G11C7/04 ,  G11C11/4078 ,  G11C29/12

摘要： A memory subsystem package has a memory controller interface ASIC (application specific integrated circuit) and a plurality of memory modules. The ASIC has a bi-directional serial protocol i2C communication bus to off chip drivers for monitoring temperature and for adjusting the environment surrounding the package by controlling fans using fan switches and variable voltage controls. In addition there is provided an Alternating Current Built in Self Test (AC. BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test for that ASIC enabling writing of pseudo-random patterns to memory, reading them back and comparing the expected results at hardware speeds. Vref can be made to vary across its allowable range during AC self test to provide improved coverage. The system monitors Vddq during normal system operation using an ADC. The system varies Vref as a function of Vddq, using a combination of a DAC and ADC. The system varies Vref as a function of Vddq, such that Vref=1/m*Vddq+OFFSET, where m can be 1, 2, 4, or 8, and where OFFSET can be positive or negative ranging from 1/n*Vddq to n−1/n*Vddq, where n is the voltage granularity of the DAC.

摘要翻译： 存储器子系统包具有存储器控制器接口ASIC（专用集成电路）和多个存储器模块。 ASIC具有双向串行协议i2C通信总线到芯片外驱动器，用于监控温度，并通过使用风扇开关和可变电压控制控制风扇来调节封装周围的环境。 此外，还提供了具有可变数据接收器电压参考的内置自检（AC。BIST）的交流电，用于为该ASIC执行高速AC存储器子系统自检，使得能够将伪随机模式写入存储器，读取它们 并以硬件速度比较预期结果。 在AC自检期间，可以使Vref在其允许范围内变化，以提供更好的覆盖。 系统使用ADC在系统正常运行期间监视Vddq。 该系统使用DAC和ADC的组合，将Vdd变为Vddq的函数。 该系统将Vref作为Vddq的函数，使得Vref = 1 / m * Vddq + OFFSET，其中m可以是1,2,4或8，并且其中OFFSET可以是正或负范围从1 / n * Vddq 到n-1 / n * Vddq，其中n是DAC的电压粒度。

公开(公告)号：US20080235444A1

公开(公告)日：2008-09-25

申请号：US11689647

申请日：2007-03-22

申请人： Kevin C. Gower ,  Thomas J. Griffin ,  Kirk D. Lamb ,  Dustin J. VanStee

发明人： Kevin C. Gower ,  Thomas J. Griffin ,  Kirk D. Lamb ,  Dustin J. VanStee

IPC分类号： G06F12/00

CPC分类号： G11C7/1045 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003

摘要： A system and method for providing SDRAM mode register shadowing in a memory system. A system includes a memory interface device adapted for use in a memory system. The memory interface device includes an interface to one or more ranks of memory devices, and each memory device includes one or more types of mode registers. The memory interface device also includes an interface to a memory bus for receiving commands from a memory controller. The commands include a mode register set command specifying a new mode register setting for one or more ranks of memory devices and a mode register type. The memory interface device further includes a mode register shadow module to capture settings applied to the mode registers. The module includes a shadow register for each type of mode register and a shadow log for each type of mode register. The module also includes mode register shadow logic to detect a mode register set command, to store the new mode register setting in the shadow register corresponding to the specified mode register type, and to set one or more bits in the shadow log corresponding to the specified mode register type to indicate which of the ranks of memory devices have been programmed with the new mode register setting.

摘要翻译： 一种用于在存储器系统中提供SDRAM模式寄存器阴影的系统和方法。 系统包括适于在存储器系统中使用的存储器接口设备。 存储器接口设备包括到一个或多个存储器设备等级的接口，并且每个存储器设备包括一种或多种类型的模式寄存器。 存储器接口设备还包括到存储器总线的接口，用于从存储器控制器接收命令。 这些命令包括指定用于一个或多个存储器件级别的模式寄存器设置的模式寄存器设置命令和模式寄存器类型。 存储器接口设备还包括模式寄存器阴影模块，用于捕获应用于模式寄存器的设置。 该模块包括每种类型的模式寄存器的影子寄存器和每种类型的模式寄存器的影子日志。 该模块还包括模式寄存器阴影逻辑，用于检测模式寄存器设置命令，将新模式寄存器设置存储在与指定模式寄存器类型相对应的影子寄存器中，并设置与指定的对应的影子日志中的一个或多个位 模式寄存器类型，以指示使用新模式寄存器设置来编程存储器件的哪些等级。

公开(公告)号：US20080307374A1

公开(公告)日：2008-12-11

申请号：US11758277

申请日：2007-06-05

申请人： James C. Gregerson ,  Leonard M. Greenberg ,  Steven J. Hnatko ,  Kirk D. Lamb ,  James H. McCullen

发明人： James C. Gregerson ,  Leonard M. Greenberg ,  Steven J. Hnatko ,  Kirk D. Lamb ,  James H. McCullen

IPC分类号： G06F9/45

CPC分类号： G06F17/5077 ,  G06F17/5031

摘要： A logical design including multiple logical blocks is mapped onto an integrated circuit chip. A chip level floor plan is created on the chip, including temporary areas on the chip set aside for accommodating logical blocks having logical content including timing requirements based on the logical design. The temporary areas are translated into physical cells on the chip with pins assigned for inputs and outputs for the logical blocks. The logical blocks are mapped to the physical cells on the chip in a time sensitive manner using timing assertions to form temporary logical partitions. Blocks on the chip, including the temporary logical partitions, are connected based on the timing assertions. A timing analysis is performed on the chip to determine timing slack associated with each temporary logical partition. A determination is made whether the timing slack is acceptable. If the timing slack is not acceptable, the slack is apportioned for, and apportioned slack information is fed back in the form of timing assertions. Mapping, connecting, performing a timing analysis, and apportioning for slack are repeated until the timing slack associated with each temporary logical partition is determined to be acceptable.

摘要翻译： 包括多个逻辑块的逻辑设计被映射到集成电路芯片上。 在芯片上创建芯片级平面图，包括芯片上的临时区域，用于容纳具有逻辑内容的逻辑块，包括基于逻辑设计的定时要求。 临时区域被转换为芯片上的物理单元，其中分配有针对逻辑块的输入和输出的引脚。 逻辑块以时间敏感的方式映射到芯片上的物理单元，使用定时断言来形成临时逻辑分区。 基于定时断言连接芯片上的块，包括临时逻辑分区。 在芯片上执行定时分析以确定与每个临时逻辑分区相关联的定时松弛。 确定定时松弛是否可接受。 如果时间松弛是不能接受的，则该松弛被分摊，并且分时的松弛信息以定时断言的形式被反馈。 重复映射，连接，执行定时分析和分配分配，直到确定与每个临时逻辑分区相关联的定时松弛是可接受的。

公开(公告)号：US06807650B2

公开(公告)日：2004-10-19

申请号：US10161377

申请日：2002-06-03

申请人： Kirk D. Lamb ,  Dustin J. VanStee

发明人： Kirk D. Lamb ,  Dustin J. VanStee

IPC分类号： G06F1750

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/2254

摘要： A memory interface device uses a driver impedance adjustment engine with state machine for off chip driver (OCD) calibration which is used to set the driver voltage levels of the DRAM memory module or DIMM of the JEDEC DDR-II standard type. By adjusting the pull-up drive strength and pull-down drive strength, the output voltage levels and the rise times can be optimized to find the minimal signal swing that is still immune to noise, while not degrading the data eye significantly. The state machine finds the optimal setting for the DRAM Driver Impedance, using both DC and AC methods adjusting the value of the driver impedance through a master ASIC, and then sampling the known value sent back from the DRAM. The state machine will stop when the optimal value of the driver impedance is found and automates the process of detecting the optimal driver impedance and configuring the DRAM module or DIMM accordingly. The ASIC circuit and method use a data strobe, not only as strobe, but as data input during OCD calibration. Optimal driver impedance setting of a DDR-II DRAM is detected in a DC mode. Using AC-BIST the optimal driver impedance setting can be adjusted and optimized to account for AC timing influences such as coupled noise, data dependent jitter, and intersymbol interference.

摘要翻译： 存储器接口设备使用具有状态机的驱动器阻抗调节引擎用于片外驱动器（OCD）校准，用于设置JEDEC DDR-II标准类型的DRAM存储器模块或DIMM的驱动器电压电平。 通过调节上拉驱动强度和下拉驱动强度，可以优化输出电压电平和上升时间，以发现仍然免受噪声影响的最小信号摆幅，同时不会显着降低数据的眼睛。 状态机通过主控ASIC调整驱动器阻抗值，同时使用直流和交流方法，找到DRAM驱动阻抗的最佳设置，然后对从DRAM发回的已知值进行采样。 当发现驱动器阻抗的最佳值时，状态机将停止，并自动执行检测最佳驱动器阻抗的过程，并相应地配置DRAM模块或DIMM。 ASIC电路和方法使用数据选通，不仅作为选通脉冲，而且用作OCD校准期间的数据输入。 在DC模式下检测到DDR-II DRAM的最佳驱动器阻抗设置。 使用AC-BIST可以调整和优化最佳驱动器阻抗设置，以考虑交流定时影响，如耦合噪声，数据相关抖动和符号间干扰。

公开(公告)号：US5282210A

公开(公告)日：1994-01-25

申请号：US891521

申请日：1992-06-01

申请人： Timothy J. Slegel ,  Charlotte A. Reed ,  Kirk D. Lamb ,  Donald H. Friedberg

发明人： Timothy J. Slegel ,  Charlotte A. Reed ,  Kirk D. Lamb ,  Donald H. Friedberg

IPC分类号： G06F13/36 ,  G06F13/38 ,  G06F13/42 ,  H04J3/04 ,  H04L5/22 ,  H03K19/08 ,  H04L25/14

CPC分类号： H04J3/047

摘要： A time-division multiplex system is disclosed where the data from two sources is coupled over a multiplexer controller by a generator comprising an XOR gate and a pair of latches where the output of both latches are coupled to the XOR gate and an inverter at the input of each latch. One of the latches is gated by a master clock signal and the other latch is gated by a clocked signal skewed approximately one-half clock cycle.

摘要翻译： 公开了一种时分多路复用系统，其中来自两个源的数据通过多路复用器控制器由包括XOR门和一对锁存器的发生器耦合，其中两个锁存器的输出耦合到XOR门和在输入端的反相器 的每个闩锁。 一个锁存器由主时钟信号门控，另一个锁存器由大约半个时钟周期的时钟信号门控。