公开(公告)号：US20130292774A1

公开(公告)日：2013-11-07

申请号：US13465731

申请日：2012-05-07

申请人： Jan Hoentschel ,  Sven Beyer ,  Oliver Kallensee ,  Stefan Flachowsky

发明人： Jan Hoentschel ,  Sven Beyer ,  Oliver Kallensee ,  Stefan Flachowsky

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/1045 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device having raised source and drain regions is formed by forming a gate electrode structure on a semiconductor substrate, forming a first spacer structure laterally to the gate electrode structure, forming a semiconductor layer over an exposed surface of the semiconductor substrate at both sides of the gate electrode structure such that a layer portion is formed which is beveled towards the gate electrode with regard to the exposed surface of the semiconductor substrate, and forming a second spacer structure over the first spacer structure, wherein the second spacer structure covers at least a portion of the beveled layer portion.

摘要翻译： 通过在半导体衬底上形成栅电极结构形成具有凸起的源极和漏极区的半导体器件，在栅电极结构上横向形成第一间隔结构，在半导体衬底的两侧的暴露表面上形成半导体层 所述栅电极结构使得形成相对于所述半导体衬底的暴露表面朝向所述栅电极倾斜的层部分，以及在所述第一间隔结构上形成第二间隔结构，其中所述第二间隔结构覆盖至少一个 斜面层部分的一部分。

公开(公告)号：US08536036B2

公开(公告)日：2013-09-17

申请号：US12905711

申请日：2010-10-15

申请人： Sven Beyer ,  Jan Hoentschel ,  Uwe Griebenow ,  Thilo Scheiper

发明人： Sven Beyer ,  Jan Hoentschel ,  Uwe Griebenow ,  Thilo Scheiper

IPC分类号： H01L21/425 ,  H01L21/28 ,  H01L21/44

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/7848

摘要： In a process strategy for forming high-k metal gate electrode structures in an early manufacturing phase, a predoped semiconductor material may be used in order to reduce the Schottky barrier between the semiconductor material and the conductive cap material of the gate electrode structures. Due to the substantially uniform material characteristics of the predoped semiconductor material, any patterning-related non-uniformities during the complex patterning process of the gate electrode structures may be reduced. The predoped semiconductor material may be used for gate electrode structures of complementary transistors.

摘要翻译： 在用于在早期制造阶段形成高k金属栅电极结构的工艺策略中，可以使用预制半导体材料，以便减少半导体材料与栅电极结构的导电盖材料之间的肖特基势垒。 由于预制半导体材料的材料特性基本上均匀，可能会降低栅电极结构复杂构图工艺过程中任何与图案相关的不均匀性。 预制半导体材料可用于互补晶体管的栅电极结构。

公开(公告)号：US08507348B2

公开(公告)日：2013-08-13

申请号：US12939282

申请日：2010-11-04

申请人： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

发明人： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

IPC分类号： H01L21/336

CPC分类号： H01L29/788 ,  G11C16/0425 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

公开(公告)号：US08445344B2

公开(公告)日：2013-05-21

申请号：US12787461

申请日：2010-05-26

申请人： Richard Carter ,  Falk Graetsch ,  Martin Trentzsch ,  Sven Beyer ,  Berthold Reimer ,  Robert Binder ,  Boris Bayha

发明人： Richard Carter ,  Falk Graetsch ,  Martin Trentzsch ,  Sven Beyer ,  Berthold Reimer ,  Robert Binder ,  Boris Bayha

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

摘要： Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.

摘要翻译： 在基本上相同的构造的基础上对N沟道晶体管和P沟道晶体管的复杂的栅电极结构进行构图，然而，可以在早期制造阶段完成功函数调整。 为此，在将期望的功函数金属物质并入高k电介质材料中之后去除扩散层和覆盖层材料，随后沉积公共栅层堆叠并随后构图。

公开(公告)号：US08247275B2

公开(公告)日：2012-08-21

申请号：US12898958

申请日：2010-10-06

申请人： Jan Hoentschel ,  Sven Beyer ,  Uwe Griebenow

发明人： Jan Hoentschel ,  Sven Beyer ,  Uwe Griebenow

IPC分类号： H01L21/00

CPC分类号： H01L29/045 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

摘要： Non-planar transistors, such as FINFETs, may be formed on the basis of a globally strained semiconductor material, thereby preserving a high uniaxial strain component in the resulting semiconductor fins. In this manner, a significant performance enhancement may be achieved without adding process complexity when implementing FINFET transistors.

摘要翻译： 可以在全局应变半导体材料的基础上形成诸如FINFET的非平面晶体管，从而在所得到的半导体鳍片中保持高的单轴应变分量。 以这种方式，当实现FINFET晶体管时，可以实现显着的性能增强，而不会增加工艺复杂性。

公开(公告)号：US08232188B2

公开(公告)日：2012-07-31

申请号：US12905440

申请日：2010-10-15

申请人： Sven Beyer ,  Klaus Hempel ,  Thilo Scheiper ,  Stefanie Steiner

发明人： Sven Beyer ,  Klaus Hempel ,  Thilo Scheiper ,  Stefanie Steiner

IPC分类号： H01L27/092 ,  H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66545

摘要： In a replacement gate approach in sophisticated semiconductor devices, the place-holder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal may be selectively formed in the resulting gate opening, thereby providing superior process conditions in adjusting a respective work function of gate electrode structures of different type. In one illustrative embodiment, the separate forming of gate openings in gate electrode structures of different type may be based on a mask material that is provided in a gate layer stack.

摘要翻译： 在复杂半导体器件中的替代栅极方法中，分别去除不同类型的栅电极结构的放置保持材料。 此外，可以在所得到的栅极开口中选择性地形成电极金属，从而在调整不同类型的栅电极结构的各自的功函数方面提供优异的工艺条件。 在一个说明性实施例中，在不同类型的栅极电极结构中单独形成栅极开口可以基于设置在栅极层叠层中的掩模材料。

公开(公告)号：US08198152B2

公开(公告)日：2012-06-12

申请号：US12917700

申请日：2010-11-02

申请人： Sven Beyer ,  Jan Hoentschel ,  Thilo Scheiper ,  Uwe Griebenow

发明人： Sven Beyer ,  Jan Hoentschel ,  Thilo Scheiper ,  Uwe Griebenow

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/425 ,  H01L21/38

CPC分类号： H01L21/823807 ,  H01L21/28123 ,  H01L21/823828 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： In sophisticated semiconductor devices, a replacement gate approach may be applied, in which a channel semiconductor material may be provided through the gate opening prior to forming the gate dielectric material and the electrode metal. In this manner, specific channel materials may be provided in a late manufacturing stage for different transistor types, thereby providing superior transistor performance and superior flexibility in adjusting the electronic characteristics of the transistors.

摘要翻译： 在复杂的半导体器件中，可以应用替代栅极方法，其中可以在形成栅极电介质材料和电极金属之前通过栅极开口提供沟道半导体材料。 以这种方式，可以在后期制造阶段为不同的晶体管类型提供特定的沟道材料，从而在调整晶体管的电子特性方面提供优异的晶体管性能和优异的灵活性。

公开(公告)号：US20120086056A1

公开(公告)日：2012-04-12

申请号：US13188745

申请日：2011-07-22

申请人： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

发明人： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

IPC分类号： H01L21/28 ,  H01L29/78

CPC分类号： H01L29/42376 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/42364 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

摘要： In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.

摘要翻译： 在复杂的半导体器件中，可以通过形成底切门配置来实现在早期制造阶段中提供的诸如高k电介质材料和含金属电极材料的敏感栅极材料的封装。 为此，在栅极层叠层的基本图案化之后施加湿化学蚀刻序列，其中至少以交替的方式进行基于臭氧和基于氢氟酸的工艺步骤，从而实现基本上自限制的去除行为 。

公开(公告)号：US20110211394A1

公开(公告)日：2011-09-01

申请号：US12939282

申请日：2010-11-04

申请人： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

发明人： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L29/788 ,  G11C16/0425 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

摘要翻译： 可以在自对准电荷存储区域的基础上提供用于半导体器件中的闪存区域的存储晶体管。 为此，可以在一些说明性实施例中提供浮动间隔元件，而在其他情况下，在替换栅极方法期间，电荷存储区域可以以自对准方式有效地嵌入电极材料中。 因此，可以不再需要用于图案化电荷存储区域的附加复杂光刻工艺，可以实现增强的位密度。

公开(公告)号：US20110210427A1

公开(公告)日：2011-09-01

申请号：US12917870

申请日：2010-11-02

申请人： Jan Hoentschel ,  Sven Beyer ,  Uwe Griebenow ,  Thilo Scheiper

发明人： Jan Hoentschel ,  Sven Beyer ,  Uwe Griebenow ,  Thilo Scheiper

IPC分类号： H01L29/06 ,  H01L21/3115

CPC分类号： H01L21/3081 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7849

摘要： In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors.

摘要翻译： 在复杂的半导体器件中，通过使用刚性掩模材料可以在形成浅沟槽隔离期间实质上保留全局应变半导体层的初始应变分量，这可以有效地避免或减少图案化隔离沟槽时半导体岛的变形 。 因此，可以提供具有高内应力水平的选定区域，而不考虑高度 - 长度的纵横比，这可能限制在常规方法中全局应变半导体层的应用。 此外，在一些说明性实施例中，除了高应变活性区域之外，还可以提供基本上松弛的应变状态或逆应变类型的有源区，从而实现用于形成互补晶体管的有效的工艺策略。