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15 条记录 (耗时 0.017 秒)

    ENHANCED ETCH STOP CAPABILITY DURING PATTERNING OF SILICON NITRIDE INCLUDING LAYER STACKS BY PROVIDING A CHEMICALLY FORMED OXIDE LAYER DURING SEMICONDUCTOR PROCESSING
    4.
    发明申请
    ENHANCED ETCH STOP CAPABILITY DURING PATTERNING OF SILICON NITRIDE INCLUDING LAYER STACKS BY PROVIDING A CHEMICALLY FORMED OXIDE LAYER DURING SEMICONDUCTOR PROCESSING 有权
    通过在半导体加工过程中提供化学氧化物层，在含氮层包括层堆叠的过程中增强蚀刻阻挡能力

    公开(公告)号：US20100304542A1

    公开(公告)日：2010-12-02

    申请号：US12785849

    申请日：2010-05-24

    申请人： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

    发明人： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L29/513 ,  H01L29/66583 ,  H01L29/7833

    摘要： A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material.

    摘要翻译： 栅极电极结构可以基于氮化硅帽材料与非常薄且均匀的基于氧化硅的蚀刻停止材料组合形成，其可以基于化学驱动的氧化工艺形成。 由于厚度减小，可以避免例如在门图案化之后的湿化学清洁过程期间显着的材料侵蚀，从而不会过度影响进一步的加工，例如关于形成嵌入式应变诱导半导体合金， 同时在去除氮化硅帽材料期间提供期望的蚀刻停止能力。

    Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing
    6.
    发明授权
    Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing 有权
    通过在半导体处理期间提供化学形成的氧化物层，在包括层堆叠的氮化硅图案化期间增强蚀刻停止能力

    公开(公告)号：US08283232B2

    公开(公告)日：2012-10-09

    申请号：US12785849

    申请日：2010-05-24

    申请人： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

    发明人： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L29/513 ,  H01L29/66583 ,  H01L29/7833

    摘要： A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material.

    摘要翻译： 栅极电极结构可以基于氮化硅帽材料与非常薄且均匀的基于氧化硅的蚀刻停止材料组合形成，其可以基于化学驱动的氧化工艺形成。 由于厚度减小，可以避免例如在门图案化之后的湿化学清洁过程期间显着的材料侵蚀，从而不会过度影响进一步的加工，例如关于形成嵌入式应变诱导半导体合金， 同时在去除氮化硅帽材料期间提供期望的蚀刻停止能力。

    Method of forming layers of oxide on a surface of a substrate
    7.
    发明授权
    Method of forming layers of oxide on a surface of a substrate 失效
    在基板的表面上形成氧化物层的方法

    公开(公告)号：US06703278B2

    公开(公告)日：2004-03-09

    申请号：US10208308

    申请日：2002-07-30

    申请人： Karsten Wieczorek ,  Falk Graetsch ,  Stephan Kruegel

    发明人： Karsten Wieczorek ,  Falk Graetsch ,  Stephan Kruegel

    IPC分类号： H01L21336

    CPC分类号： H01L21/823462 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31111 ,  H01L21/3144 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

    摘要： A method of forming oxide layers of different thickness on a substrate is described, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices.

    摘要翻译： 描述了在衬底上形成不同厚度的氧化物层的方法，其中氧化物层优选用作场效应晶体管的栅极绝缘层。 与常规处理相比，该方法允许形成具有减少数量的掩模步骤的非常薄的高质量氧化物层，其中厚度差可以保持在十分之几纳米的范围内。 该方法基本上消除了任何高温氧化，并且也与用于复杂半导体器件中的栅极介电沉积的大多数化学气相沉积技术相兼容。

    METHOD FOR ENCAPSULATING A HIGH-K GATE STACK BY FORMING A LINER AT TWO DIFFERENT PROCESS TEMPERATURES
    8.
    发明申请
    METHOD FOR ENCAPSULATING A HIGH-K GATE STACK BY FORMING A LINER AT TWO DIFFERENT PROCESS TEMPERATURES 有权
    通过在两个不同的工艺温度下形成衬里来封装高K门盖的方法

    公开(公告)号：US20090242999A1

    公开(公告)日：2009-10-01

    申请号：US12355250

    申请日：2009-01-16

    申请人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

    发明人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/31

    CPC分类号： H01L21/31604 ,  H01L21/28176 ,  H01L21/28202 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

    摘要： Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.

    摘要翻译： 包括高k电介质材料的栅极堆叠的封装可以基于以两个沉积工艺的顺序沉积的氮化硅材料来实现，其中第一工艺可以在适度低的工艺 温度，从而钝化敏感表面，而不会不适当地污染它们，而在第二沉积过程中，与传统的ALD或多层沉积技术相比，可以使用适度高的工艺温度来提供增强的材料特性和减小的总循环时间。

    Method of forming a low leakage dielectric layer providing an increased capacitive coupling
    9.
    发明授权
    Method of forming a low leakage dielectric layer providing an increased capacitive coupling 有权
    形成提供增加的电容耦合的低漏电介质层的方法

    公开(公告)号：US06812159B2

    公开(公告)日：2004-11-02

    申请号：US10420635

    申请日：2003-04-22

    申请人： Karsten Wieczorek ,  Falk Graetsch ,  Lutz Herrmann

    发明人： Karsten Wieczorek ,  Falk Graetsch ,  Lutz Herrmann

    IPC分类号： H01L2131

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31116 ,  H01L21/3115 ,  H01L29/518

    摘要： A method of forming a dielectric layer that may be used as a dielectric separating a gate electrode from a channel region of a field effect transistor is provided which allows a high capacitive coupling while still maintaining a low leakage current level. This is achieved by introducing a dopant, for example nitrogen, that increases the resistance of the dielectric layer by means of low energy plasma irradiation, wherein an initial layer thickness is selected to substantially avoid penetration of the dopant into the underlying material. Subsequently, dielectric material is removed by an atomic layer etch to finally obtain the required design thickness.

    摘要翻译： 提供一种形成可用作将场电极与场效应晶体管的沟道区分离的介质的电介质层的方法，其允许高电容耦合同时仍然保持低的漏电流水平。 这通过引入通过低能量等离子体照射来增加电介质层的电阻的掺杂剂例如氮来实现，其中选择初始层厚度以基本上避免掺杂剂渗透到下面的材料中。 随后，通过原子层蚀刻去除电介质材料，以最终获得所需的设计厚度。

    Method for encapsulating a high-K gate stack by forming a liner at two different process temperatures
    10.
    发明授权
    Method for encapsulating a high-K gate stack by forming a liner at two different process temperatures 有权
    通过在两个不同的工艺温度下形成衬套来封装高K栅极堆叠的方法

    公开(公告)号：US07897450B2

    公开(公告)日：2011-03-01

    申请号：US12355250

    申请日：2009-01-16

    申请人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

    发明人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

    IPC分类号： H01L21/8249

    CPC分类号： H01L21/31604 ,  H01L21/28176 ,  H01L21/28202 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

    摘要： Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.

    摘要翻译： 包括高k电介质材料的栅极堆叠的封装可以基于以两个沉积工艺的顺序沉积的氮化硅材料来实现，其中第一工艺可以在适度低的工艺 温度，从而钝化敏感表面，而不会不适当地污染它们，而在第二沉积过程中，与传统的ALD或多层沉积技术相比，可以使用适度高的工艺温度来提供增强的材料特性和减小的总循环时间。