公开(公告)号：US08445344B2

公开(公告)日：2013-05-21

申请号：US12787461

申请日：2010-05-26

申请人： Richard Carter ,  Falk Graetsch ,  Martin Trentzsch ,  Sven Beyer ,  Berthold Reimer ,  Robert Binder ,  Boris Bayha

发明人： Richard Carter ,  Falk Graetsch ,  Martin Trentzsch ,  Sven Beyer ,  Berthold Reimer ,  Robert Binder ,  Boris Bayha

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

摘要： Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.

摘要翻译： 在基本上相同的构造的基础上对N沟道晶体管和P沟道晶体管的复杂的栅电极结构进行构图，然而，可以在早期制造阶段完成功函数调整。 为此，在将期望的功函数金属物质并入高k电介质材料中之后去除扩散层和覆盖层材料，随后沉积公共栅层堆叠并随后构图。

公开(公告)号：US20120086056A1

公开(公告)日：2012-04-12

申请号：US13188745

申请日：2011-07-22

申请人： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

发明人： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

IPC分类号： H01L21/28 ,  H01L29/78

CPC分类号： H01L29/42376 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/42364 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

摘要： In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.

摘要翻译： 在复杂的半导体器件中，可以通过形成底切门配置来实现在早期制造阶段中提供的诸如高k电介质材料和含金属电极材料的敏感栅极材料的封装。 为此，在栅极层叠层的基本图案化之后施加湿化学蚀刻序列，其中至少以交替的方式进行基于臭氧和基于氢氟酸的工艺步骤，从而实现基本上自限制的去除行为 。

公开(公告)号：US20090242999A1

公开(公告)日：2009-10-01

申请号：US12355250

申请日：2009-01-16

申请人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

发明人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/31

CPC分类号： H01L21/31604 ,  H01L21/28176 ,  H01L21/28202 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.

摘要翻译： 包括高k电介质材料的栅极堆叠的封装可以基于以两个沉积工艺的顺序沉积的氮化硅材料来实现，其中第一工艺可以在适度低的工艺 温度，从而钝化敏感表面，而不会不适当地污染它们，而在第二沉积过程中，与传统的ALD或多层沉积技术相比，可以使用适度高的工艺温度来提供增强的材料特性和减小的总循环时间。

公开(公告)号：US06812159B2

公开(公告)日：2004-11-02

申请号：US10420635

申请日：2003-04-22

申请人： Karsten Wieczorek ,  Falk Graetsch ,  Lutz Herrmann

发明人： Karsten Wieczorek ,  Falk Graetsch ,  Lutz Herrmann

IPC分类号： H01L2131

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31116 ,  H01L21/3115 ,  H01L29/518

摘要： A method of forming a dielectric layer that may be used as a dielectric separating a gate electrode from a channel region of a field effect transistor is provided which allows a high capacitive coupling while still maintaining a low leakage current level. This is achieved by introducing a dopant, for example nitrogen, that increases the resistance of the dielectric layer by means of low energy plasma irradiation, wherein an initial layer thickness is selected to substantially avoid penetration of the dopant into the underlying material. Subsequently, dielectric material is removed by an atomic layer etch to finally obtain the required design thickness.

摘要翻译： 提供一种形成可用作将场电极与场效应晶体管的沟道区分离的介质的电介质层的方法，其允许高电容耦合同时仍然保持低的漏电流水平。 这通过引入通过低能量等离子体照射来增加电介质层的电阻的掺杂剂例如氮来实现，其中选择初始层厚度以基本上避免掺杂剂渗透到下面的材料中。 随后，通过原子层蚀刻去除电介质材料，以最终获得所需的设计厚度。

公开(公告)号：US20100327373A1

公开(公告)日：2010-12-30

申请号：US12787461

申请日：2010-05-26

申请人： Richard Carter ,  Falk Graetsch ,  Martin Trentzsch ,  Sven Beyer ,  Berthold Reimer ,  Robert Binder ,  Boris Bayha

发明人： Richard Carter ,  Falk Graetsch ,  Martin Trentzsch ,  Sven Beyer ,  Berthold Reimer ,  Robert Binder ,  Boris Bayha

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

摘要： Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.

摘要翻译： 在基本上相同的构造的基础上对N沟道晶体管和P沟道晶体管的复杂的栅电极结构进行构图，然而，可以在早期制造阶段完成功函数调整。 为此，在将期望的功函数金属物质并入高k电介质材料中之后去除扩散层和覆盖层材料，随后沉积公共栅层堆叠并随后构图。

公开(公告)号：US06703278B2

公开(公告)日：2004-03-09

申请号：US10208308

申请日：2002-07-30

申请人： Karsten Wieczorek ,  Falk Graetsch ,  Stephan Kruegel

发明人： Karsten Wieczorek ,  Falk Graetsch ,  Stephan Kruegel

IPC分类号： H01L21336

CPC分类号： H01L21/823462 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31111 ,  H01L21/3144 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

摘要： A method of forming oxide layers of different thickness on a substrate is described, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices.

摘要翻译： 描述了在衬底上形成不同厚度的氧化物层的方法，其中氧化物层优选用作场效应晶体管的栅极绝缘层。 与常规处理相比，该方法允许形成具有减少数量的掩模步骤的非常薄的高质量氧化物层，其中厚度差可以保持在十分之几纳米的范围内。 该方法基本上消除了任何高温氧化，并且也与用于复杂半导体器件中的栅极介电沉积的大多数化学气相沉积技术相兼容。

公开(公告)号：US07897450B2

公开(公告)日：2011-03-01

申请号：US12355250

申请日：2009-01-16

申请人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

发明人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

IPC分类号： H01L21/8249

CPC分类号： H01L21/31604 ,  H01L21/28176 ,  H01L21/28202 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.

摘要翻译： 包括高k电介质材料的栅极堆叠的封装可以基于以两个沉积工艺的顺序沉积的氮化硅材料来实现，其中第一工艺可以在适度低的工艺 温度，从而钝化敏感表面，而不会不适当地污染它们，而在第二沉积过程中，与传统的ALD或多层沉积技术相比，可以使用适度高的工艺温度来提供增强的材料特性和减小的总循环时间。

公开(公告)号：US20100304542A1

公开(公告)日：2010-12-02

申请号：US12785849

申请日：2010-05-24

申请人： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

发明人： Sven Beyer ,  Berthold Reimer ,  Falk Graetsch

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L29/513 ,  H01L29/66583 ,  H01L29/7833

摘要： A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material.

摘要翻译： 栅极电极结构可以基于氮化硅帽材料与非常薄且均匀的基于氧化硅的蚀刻停止材料组合形成，其可以基于化学驱动的氧化工艺形成。 由于厚度减小，可以避免例如在门图案化之后的湿化学清洁过程期间显着的材料侵蚀，从而不会过度影响进一步的加工，例如关于形成嵌入式应变诱导半导体合金， 同时在去除氮化硅帽材料期间提供期望的蚀刻停止能力。

公开(公告)号：US20090246371A1

公开(公告)日：2009-10-01

申请号：US12275304

申请日：2008-11-21

申请人： Fabian Koehler ,  Falk Graetsch

发明人： Fabian Koehler ,  Falk Graetsch

IPC分类号： C23C16/00

CPC分类号： H01L21/31608 ,  H01L21/0223 ,  H01L21/02271 ,  H01L21/31658 ,  H01L21/3185

摘要： A thermally activated batch process is disclosed for forming thin material layers in semiconductor devices including the establishment of an overheating temperature profile prior to actually forming a material layer, for instance, by deposition, so that a gas depletion at the centre of the substrate during the deposition process be compensated for. Thus, enhanced thickness uniformity for thin material layers in the range of 1 to 50 nanometers may be obtained without additional process time or even at a reduced process time.

摘要翻译： 公开了一种用于在半导体器件中形成薄材料层的热激活分批工艺，包括在实际形成材料层之前建立过热温度曲线，例如通过沉积，从而在基板的中心处的气体耗尽 沉积过程得到补偿。 因此，可以获得在1至50纳米范围内的薄材料层的增强的厚度均匀性，而无需额外的处理时间或甚至在缩短的处理时间。

公开(公告)号：US06723663B1

公开(公告)日：2004-04-20

申请号：US10443642

申请日：2003-05-22

申请人： Karsten Wieczorek ,  Falk Graetsch ,  Lutz Herrmann

发明人： Karsten Wieczorek ,  Falk Graetsch ,  Lutz Herrmann

IPC分类号： H01L2131

CPC分类号： H01L21/28202 ,  H01L21/3144 ,  H01L29/518

摘要： For aggressively scaled field effect transistors, nitrogen is incorporated into a base oxide layer, wherein, at an initial phase of a plasma nitridation process, the nitrogen ion density is maintained at a value so that incorporation of nitrogen into the channel region is minimized. Subsequently, when the thickness of the base oxide layer has increased, due to residual oxygen in the plasma ambient, the nitrogen ion density is increased, thereby increasing the nitridation rate. Preferably, the nitrogen ion density is controlled by varying the pressure of the plasma ambient. Moreover, a system is disclosed that allows control of the nitridation rate in response to an oxide layer thickness.

摘要翻译： 对于大规模的场效应晶体管，将氮掺入到基底氧化物层中，其中在等离子体氮化处理的初始阶段，将氮离子密度保持在一个值，使得氮进入沟道区域的值最小化。 随后，当基底氧化物层的厚度增加时，由于等离子体环境中的残余氧，氮离子密度增加，从而提高了氮化速率。 优选地，通过改变等离子体环境的压力来控制氮离子密度。 此外，公开了一种允许响应于氧化物层厚度来控制氮化速率的系统。