公开(公告)号：US20090290582A1

公开(公告)日：2009-11-26

申请号：US12295407

申请日：2007-02-20

申请人： Hiroshi Suenaga. ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Noriaki Takeda ,  Takaharu Yoshida

发明人： Hiroshi Suenaga. ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Noriaki Takeda ,  Takaharu Yoshida

IPC分类号： H04L12/56 ,  H04J3/00

CPC分类号： H04L25/14

摘要： It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal. The invention provides a signal transmission method that is characterized in that a reception side and a transmission side partition data into a plurality of data fragments and send and receive the plurality of data fragments over at least two transmission lines, in that the transmission side transmits first data fragments of the plurality of data fragments over a first transmission line of the transmission lines, transmits data packets that include header information, a second data fragment that has the same bit length as the first data fragments, and footer information over a second transmission line other than the first transmission line, and transmits the first data fragments and the second data fragments in synchronization, and in that an interrupt signal for controlling the transmission side is transmitted from the reception side to the transmission side in a time slot that is an interval between first data fragments that are adjacent on the first transmission line.

摘要翻译： 本发明的一个目的是抑制由于中断信号的传输引起的数据传输效率的下降。 本发明提供了一种信号传输方法，其特征在于，接收侧和发送侧将数据划分成多个数据片段，并通过至少两条传输线发送和接收多个数据片段，其中发送侧首先发送 在传输线的第一传输线上的多个数据片段的数据片段，通过第二传输线传输包括标题信息的数据包，具有与第一数据片段相同的位长的第二数据片段，以及页脚信息 除了第一传输线之外，并且同步地发送第一数据片段和第二数据片段，并且用于控制发送侧的中断信号在作为间隔的时隙中的从接收侧发送到发送侧 在第一传输线上相邻的第一数据片段之间。

公开(公告)号：US07242733B2

公开(公告)日：2007-07-10

申请号：US10458428

申请日：2003-06-11

申请人： Toru Iwata

发明人： Toru Iwata

IPC分类号： H04L7/00

CPC分类号： H03L7/0805 ,  H03K5/135 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0995 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0337

摘要： The clock recovery circuit includes a first oscillator and an edge detector. The first oscillator generates a plurality of clocks having different phases and a predetermined frequency. The edge detector detects two clocks, among the plurality of clocks, between edges of which an input data signal has made a transition. The first oscillator includes a plurality of delay cells connected in a ring, and outputs of the plurality of delay cells are output as the plurality of clocks. Each of the plurality of delay cells selectively delays a first-delay added input data signal or the signal output from the preceding delay cell, and outputs the selected delayed signal. The edge detector controls one delay cell among the plurality of delay cells corresponding to the result of the detection, to delay and output the first-delay added input data signal.

摘要翻译： 时钟恢复电路包括第一振荡器和边缘检测器。 第一振荡器产生具有不同相位和预定频率的多个时钟。 边缘检测器在多个时钟之间检测输入数据信号已经转换的边缘之间的两个时钟。 第一振荡器包括以环形连接的多个延迟单元，多个延迟单元的输出作为多个时钟输出。 多个延迟单元中的每一个选择性地延迟第一延迟相加的输入数据信号或从前一个延迟单元输出的信号，并输出所选择的延迟信号。 边缘检测器控制与检测结果相对应的多个延迟单元之中的一个延迟单元，以延迟和输出第一延迟相加的输入数据信号。

公开(公告)号：US07212028B2

公开(公告)日：2007-05-01

申请号：US11038436

申请日：2005-01-21

申请人： Osamu Shibata ,  Toru Iwata ,  Yoshiyuki Saito ,  Satoshi Takahashi ,  Wataru Itoh

发明人： Osamu Shibata ,  Toru Iwata ,  Yoshiyuki Saito ,  Satoshi Takahashi ,  Wataru Itoh

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0278 ,  H04L25/0292

摘要： First and second transmission lines and are connected to each other in series. A first terminator is connected to the first transmission line in parallel, and is provided externally of a semiconductor device. A second terminator is connected to the second transmission line in parallel, and is provided inside the semiconductor device. The values of the first and second terminator are adjusted so that the combined resistance value of first and second terminator and the second transmission line matches with the impedance of the first transmission line. Impedance matching of the entire transmission line can be achieved with this simple construction, thus, a stable, high quality signal can be transmitted.

摘要翻译： 第一和第二传输线并且彼此串联连接。 第一终端器并联连接到第一传输线，并且设置在半导体器件的外部。 第二终端器并联连接到第二传输线，并且设置在半导体器件的内部。 调节第一和第二终端器的值，使得第一和第二终端器和第二传输线的组合电阻值与第一传输线的阻抗匹配。 可以通过这种简单的结构实现整个传输线的阻抗匹配，从而可以传输稳定的高质量信号。

公开(公告)号：US07176708B2

公开(公告)日：2007-02-13

申请号：US10716615

申请日：2003-11-20

申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

IPC分类号： H03K19/007

CPC分类号： H04L25/493

摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

摘要翻译： 在通过电缆接收数据和时钟信号的接收机电路中，通过频率检测电路检测基于数据或时钟信号获得的信号的转变次数，并且当转换次数不大于预定的集合 输出用于复位包括在数据处理单元中的串行 - 并行转换器电路的操作的信号，以便控制接收数据的输出。 因此，在不提供上拉电阻器和下拉电阻器的情况下，可以以低功耗检测电缆的断开，并且可以提高抗噪声性能。

公开(公告)号：US07007212B2

公开(公告)日：2006-02-28

申请号：US10387132

申请日：2003-03-13

申请人： Yoshihide Komatsu ,  Toru Iwata

发明人： Yoshihide Komatsu ,  Toru Iwata

IPC分类号： G01R31/28

CPC分类号： G01R31/31716

摘要： The present invention provides a transmission device, a reception device, a test circuit and a test method, which enable internal parts of the circuit to operate at high speed, while performing inputting/outputting to/from a tester at low speed. The test circuit comprises a PLL 111 which divides the frequency of a test clock input from the tester to generate a PLL clock CKp1, a FIFO 113 which stores input data input from the tester on the test clock and outputs the data on the PLL clock CKp1, an encoder 114 which distributes bits of the input data, a driver 115 which transmits the output signal from the encoder 114 to the outside, a PLL 121 which divides the frequency of the test clock to generate a PLL clock CKp2, a decoder 124 which arranges the bits of the signal received by a receiver 123.

摘要翻译： 本发明提供了一种在低速地进行/从测试仪输入/输出的同时使得电路的内部部分能够高速运行的发送装置，接收装置，测试电路和测试方法。 测试电路包括一个PLL 111，它分频输入测试时钟的频率，产生一个PLL时钟CKp 1，一个FIFO 113，它将测试时输入的输入数据存储在测试时钟上，并输出PLL时钟上的数据 CKp 1，分配输入数据的位的编码器114，将来自编码器114的输出信号发送到外部的驱动器115，分频测试时钟的频率以产生PLL时钟CKp 2的PLL 121; 解码器124，其布置由接收器123接收的信号的位。

公开(公告)号：US20050024084A1

公开(公告)日：2005-02-03

申请号：US10855351

申请日：2004-05-28

申请人： Takashi Hirata ,  Toru Iwata

发明人： Takashi Hirata ,  Toru Iwata

IPC分类号： G05F1/56 ,  H04L25/02 ,  H03K19/003

CPC分类号： H04L25/0278 ,  G05F1/56 ,  H04L25/028 ,  H04L25/0292

摘要： A terminal resistor built in a signal-sending or signal-receiving semiconductor integrated circuit is composed of a parallel circuit of a polysilicon resistor element having excellent frequency characteristic and a P-type MOS transistor. The resistance value of the polysilicon resistor element is set so as to be an approximate value of the characteristic impedance of a transmission line to be connected. The gate voltage of the P-type MOS transistor is controlled by a gate bias voltage adjustment circuit. The resistance value of the P-type MOS transistor is variably adjusted. Variation in the resistance value of the polysilicon resistor element due to dispersion in its manufacturing process is absorbed by variably adjusting the resistance value of the P-type MOS transistor. The combined resistance value of the polysilicon resistor element and the P-type MOS transistor is adjusted with high precision just to the characteristic impedance of the transmission line. Thus, a signal-sending or signal-receiving semiconductor integrated circuit in which the terminal resistor having excellent frequency and DC characteristics is built can be obtained.

摘要翻译： 内置在信号发送或信号接收半导体集成电路中的端子电阻由具有优异频率特性的多晶硅电阻元件和P型MOS晶体管的并联电路组成。 将多晶硅电阻元件的电阻值设定为要连接的传输线的特性阻抗的近似值。 P型MOS晶体管的栅极电压由栅极偏置电压调节电路控制。 可变地调节P型MOS晶体管的电阻值。 通过可变地调节P型MOS晶体管的电阻值来吸收由于其制造过程中的分散而导致的多晶硅电阻元件的电阻值的变化。 与传输线的特性阻抗相比，多晶硅电阻元件和P型MOS晶体管的组合电阻值被高精度地调整。 因此，可以获得其中构建具有优异的频率和DC特性的端子电阻器的信号发送或信号接收半导体集成电路。

公开(公告)号：US06794912B2

公开(公告)日：2004-09-21

申请号：US10361610

申请日：2003-02-11

申请人： Takashi Hirata ,  Toru Iwata

发明人： Takashi Hirata ,  Toru Iwata

IPC分类号： H03D324

CPC分类号： H03L7/0805 ,  H03K5/133 ,  H03K5/1504 ,  H03L7/07 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/0814

摘要： A multi-phase clock transmission circuit includes: a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to the phase difference between the reference clock and the generated clock; and a delay circuit for generating a multi-phase clock based on the clock and the control signal. The clock generator generates a signal having a frequency equal to an integral multiple of the frequency of the reference clock and outputs the signal as the clock. The delay circuit has a circuit receiving the clock and including a plurality of delay elements in cascade connection each giving a delay according to the control signal to an input signal. Signals output from the plurality of delay elements are used as signals constituting the multi-phase clock.

摘要翻译： 多相时钟传输电路包括：时钟发生器，用于响应于参考时钟和所产生的时钟之间的相位差，产生与参考时钟同步的时钟和控制信号; 以及用于基于时钟和控制信号产生多相时钟的延迟电路。 时钟发生器产生具有等于参考时钟的频率的整数倍的频率的信号，并将该信号作为时钟输出。 延迟电路具有接收时钟并且包括多个级联连接的延迟元件的电路，每个延迟元件根据与输入信号的控制信号给出延迟。 将从多个延迟元件输出的信号用作构成多相时钟的信号。

公开(公告)号：US06551185B1

公开(公告)日：2003-04-22

申请号：US09647499

申请日：2000-11-07

申请人： Kunihiko Miyake ,  Yoshimasa Kikuchi ,  Toru Iwata ,  Masashi Kamada

发明人： Kunihiko Miyake ,  Yoshimasa Kikuchi ,  Toru Iwata ,  Masashi Kamada

IPC分类号： F24F7007

CPC分类号： F24F7/10 ,  F24F1/0011 ,  F24F13/15 ,  F24F2001/0037 ,  F24F2001/0051 ,  F24F2001/0055 ,  F24F2003/1632 ,  F24F2003/1682

摘要： An air intake and blowing device, comprising a blowing fan (11) such as a turbo fan capable of blowing air in all directions which is installed inside a main casing (2) provided with an air intake port (5) and an air blowing port (9) enclosing the air intake port (5), the air blowing port (9) being provided with a vortex flow creating member which creates a spiral blowing vortex air flow to form a spirally swirl-blowing air flow, and air surrounded by the blowing air flow being formed in a stable tornado flow and sucked strongly into the air intake port (5).

摘要翻译： 一种进气和吹风装置，其特征在于，包括：吹风扇（11），例如可设置在设置有进气口（5）的主壳体（2）内的全向吹风的涡轮风扇;以及吹风口 （9）包围空气吸入口（5），空气吹出口（9）设置有涡流产生部件，其形成螺旋状的涡流空气流，形成螺旋旋转吹送空气流， 吹气流形成在稳定的龙卷风中并强力吸入进气口（5）。

公开(公告)号：US06201412B1

公开(公告)日：2001-03-13

申请号：US09123902

申请日：1998-07-28

申请人： Toru Iwata ,  Hironori Akamatsu ,  Takashi Hirata

发明人： Toru Iwata ,  Hironori Akamatsu ,  Takashi Hirata

IPC分类号： H03K190175

CPC分类号： H03K19/01707

摘要： The semiconductor integrated circuit of this invention includes: a driver including a MOS transistor for driving a load; and a stabilizer for stabilizing a change in a voltage at a source of the MOS transistor due to a gate-source parasitic capacitance of the MOS transistor.

摘要翻译： 本发明的半导体集成电路包括：驱动器，其包括用于驱动负载的MOS晶体管; 以及用于稳定由于MOS晶体管的栅极 - 源极寄生电容而在MOS晶体管的源极处的电压变化的稳定器。

公开(公告)号：US6101441A

公开(公告)日：2000-08-08

申请号：US99526

申请日：1998-06-18

申请人： Toru Iwata

发明人： Toru Iwata

IPC分类号： B60K28/16 ,  F02D29/02 ,  F02D33/00 ,  F02D41/02 ,  F02D41/04 ,  F02D41/30

CPC分类号： F02D41/021 ,  B60K28/16 ,  F02D33/00 ,  F02D41/3076 ,  B60W2710/0622 ,  F02D41/3029

摘要： An engine for a vehicle which selectively performs uniform combustion wherein an air-fuel mixture uniformly spread in the combustion chamber is burnt and stratified combustion wherein an air-fuel mixture converged to a part of the combustion chamber is burnt, is combined with a drive force controller for suppressing a slip of a vehicle drive wheel by reducing the engine output. At the end of drive force reduction control, it is determined whether the engine is in the stratified combustion condition or the uniform combustion condition. When it is in the stratified combustion condition, uniform combustion is first performed for a predetermined time, and then stratified combustion is performed. In this way, the combustion is prevented from becoming instable when the drive force reduction control is terminated.

摘要翻译： 一种用于车辆的发动机，其选择性地执行均匀燃烧，其中在燃烧室中均匀扩散的空气 - 燃料混合物被燃烧并分层燃烧，其中会聚到燃烧室的一部分的空气燃料混合物被燃烧，与驱动力 通过减少发动机输出来抑制车辆驱动轮的滑动的控制器。 在减速控制结束时，确定发动机是处于分层燃烧状态还是均匀燃烧状态。 当处于分层燃烧状态时，首先进行均匀燃烧预定时间，然后进行分层燃烧。 以这种方式，当停止驱动力降低控制时，防止燃烧变得不稳定。