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156 条记录 (耗时 0.041 秒)

    Gate protection for a MOSFET
    53.
    发明授权
    Gate protection for a MOSFET 失效
    MOSFET的栅极保护

    公开(公告)号：US4616243A

    公开(公告)日：1986-10-07

    申请号：US621682

    申请日：1984-06-18

    申请人： Osamu Minato ,  Toshio Sasaki ,  Toshiaki Masuhara

    发明人： Osamu Minato ,  Toshio Sasaki ,  Toshiaki Masuhara

    IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L27/06

    CPC分类号： H01L27/0266

    摘要： This invention relates to a protection device of a semiconductor device. The present invention can prevent the drop of a gate breakdown voltage due to miniaturization of a device without impeding the high speed performance of the circuit attached thereto. The invention improves the voltage that can be applied to the input terminal of the device by reducing the surface breakdown voltage of a surface breakdown type MOS transistor, which is a principal member of a protection device, and reducing the resistance after the breakdown. This can be accomplished, for example, by increasing the concentration of a region in which the MOS transistor is disposed, by reducing the depth of the region, and so forth.

    摘要翻译： 本发明涉及半导体装置的保护装置。 本发明可以防止由于器件的小型化导致的栅极击穿电压的下降，而不会妨碍附接到其上的电路的高速性能。 本发明通过降低作为保护装置的主要部件的表面击穿型MOS晶体管的表面击穿电压并且降低击穿之后的电阻来提高可施加到器件的输入端子的电压。 这可以通过例如通过降低区域的深度等来增加其中配置MOS晶体管的区域的浓度来实现。

    Semiconductor integrated circuit
    54.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US4609835A

    公开(公告)日：1986-09-02

    申请号：US471130

    申请日：1983-03-01

    申请人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki

    发明人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki

    IPC分类号： G11C11/412 ,  H01L27/06 ,  H01L27/085 ,  H01L27/11 ,  G11C11/40 ,  H01L27/04 ,  H01L29/78 ,  H03K19/094

    CPC分类号： H01L27/0688 ,  G11C11/412 ,  H01L27/085 ,  H01L27/1104 ,  H01L27/1112

    摘要： Disclosed is a semiconductor integrated circuit which comprises an n-type silicon substrate, a p-type well region having an opening at a part thereof, which is formed on the surface portion of the substrate, an MOS transistor formed in the p-type region and a resistance layer extended from the drain region of the MOS transistor to the opening of the p-type well region through a insulating film formed on the surface of the substrate, in which the drain region of the MOS transistor is electrically connected to the silicon substrate through the resistance layer so that a current is supplied to the MOS transistor.

    摘要翻译： 公开了一种半导体集成电路，其包括n型硅衬底，形成在衬底的表面部分上的具有开口的p型阱区，形成在p型区域中的MOS晶体管 以及电阻层，其通过形成在所述衬底的表面上的绝缘膜从所述MOS晶体管的漏极区延伸到所述p型阱区的开口，其中所述MOS晶体管的漏极区域与所述硅 衬底通过电阻层，以便向MOS晶体管提供电流。

    Process for producing highly stereoregular .alpha.-olefin polymers
    56.
    发明授权
    Process for producing highly stereoregular .alpha.-olefin polymers 失效
    制备高度立构规则的α-烯烃聚合物的方法

    公开(公告)号：US4412049A

    公开(公告)日：1983-10-25

    申请号：US456560

    申请日：1983-01-10

    申请人： Akinobu Shiga ,  Yukio Naito ,  Toshio Sasaki ,  Junpei Kojima ,  Hiroshi Yoshioka

    发明人： Akinobu Shiga ,  Yukio Naito ,  Toshio Sasaki ,  Junpei Kojima ,  Hiroshi Yoshioka

    IPC分类号： C08F4/64 ,  C08F10/00 ,  C08F4/02 ,  C08F10/06

    CPC分类号： C08F10/00

    摘要： A process for producing highly stereoregular .alpha.-olefin polymers which comprises polymerizing .alpha.-olefins in the presence of a catalyst system comprising:(A) a solid catalyst obtained by contact reaction between(a) a solid product prepared by reacting an organo-magnesium compound with at least one of halogenated silicon compound (I) and halogenated aluminum compound (II) in a solvent and(b) a titanium compound having both titanium-aryloxy and titanium-halogen linkages, and(B) an organo-aluminum compound as an activating agent.

    摘要翻译： 一种制备高度立构规整的α-烯烃聚合物的方法，其包括在催化剂体系存在下聚合α-烯烃，该催化剂体系包含：（A）通过以下步骤获得的固体催化剂：（a）通过使有机镁化合物 与卤化硅化合物（I）和卤化铝化合物（II）中的至少一种在溶剂中反应，和（b）具有钛 - 芳氧基和钛 - 卤素键的钛化合物，和（B）有机铝化合物 活化剂。

    LEAD FRAME AND A METHOD OF MANUFACTURING THE SAME
    59.
    发明申请
    LEAD FRAME AND A METHOD OF MANUFACTURING THE SAME 审中-公开
    引导框架及其制造方法

    公开(公告)号：US20080311703A1

    公开(公告)日：2008-12-18

    申请号：US12194001

    申请日：2008-08-19

    申请人： Fujio Ito ,  Hiromichi Suzuki ,  Toshio Sasaki

    发明人： Fujio Ito ,  Hiromichi Suzuki ,  Toshio Sasaki

    IPC分类号： H01L21/82

    CPC分类号： H01L23/49541 ,  H01L21/4842 ,  H01L23/49558 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead groups which adjoin among four inner lead groups corresponding to each side of the bar lead, and was connected with the bar lead, and a tape member joined to the tip part of each inner lead, a bar lead, and a corner part lead are included. Since the corner part lead is formed as an object for reinforcement of a frame body between adjoining inner lead groups, the rigidity of the lead frame can be increased.

    摘要翻译： 多个内部引线，多个外部引线，每个外部引线与内部引线中的每一个形成一个，方形环形状的引脚布置在多个内部引线内;角部引线，其设置在内部引线之间 所述内引线组的与所述棒引线的每一侧相对应的四个内引线组中相邻的所述内引线组的端部与所述引线连接，以及与所述内引线的前端接合的带部件， 并包括角落部分铅。 由于角部引线形成为在相邻的内引线组之间加强框架体的对象，所以可以提高引线框架的刚性。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    60.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号：US20070215952A1

    公开(公告)日：2007-09-20

    申请号：US11614619

    申请日：2006-12-21

    申请人： Osamu OZAWA ,  Toshio Sasaki ,  Ryo Mori ,  Takashi Kuraishi ,  Yoshihiko Yasu ,  Koichiro Ishibashi

    发明人： Osamu OZAWA ,  Toshio Sasaki ,  Ryo Mori ,  Takashi Kuraishi ,  Yoshihiko Yasu ,  Koichiro Ishibashi

    IPC分类号： H01L29/76

    CPC分类号： H01L27/1203 ,  H01L21/823857

    摘要： The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.

    摘要翻译： 半导体集成电路具有所谓的SOI型第一MOS晶体管（MNtk，MPtk）和第二MOS晶体管（MNtn，MPtn）。 第一MOS晶体管具有比第二MOS晶体管更厚的栅极隔离膜。 第一和第二MOS晶体管构成电源可中断电路（6）和电源不间断电路（7）。 电源中断电路具有构成源极线（VDD）和接地线（VSS）之间的电源开关（10）的第一MOS晶体管，以及与电源开关串联连接的第二MOS晶体管。 构成功率开关的第一MOS晶体管的栅极控制信号的幅度比第二MOS晶体管的幅度大。 这使得能够实现与SOI原理的SOI型半导体集成电路的器件隔离结构相当的高度灵活性的电源切断控制。