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156 条记录 (耗时 0.026 秒)

    Gate protection for a MOSFET
    1.
    发明授权
    Gate protection for a MOSFET 失效
    MOSFET的栅极保护

    公开(公告)号：US4616243A

    公开(公告)日：1986-10-07

    申请号：US621682

    申请日：1984-06-18

    申请人： Osamu Minato ,  Toshio Sasaki ,  Toshiaki Masuhara

    发明人： Osamu Minato ,  Toshio Sasaki ,  Toshiaki Masuhara

    IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L27/06

    CPC分类号： H01L27/0266

    摘要： This invention relates to a protection device of a semiconductor device. The present invention can prevent the drop of a gate breakdown voltage due to miniaturization of a device without impeding the high speed performance of the circuit attached thereto. The invention improves the voltage that can be applied to the input terminal of the device by reducing the surface breakdown voltage of a surface breakdown type MOS transistor, which is a principal member of a protection device, and reducing the resistance after the breakdown. This can be accomplished, for example, by increasing the concentration of a region in which the MOS transistor is disposed, by reducing the depth of the region, and so forth.

    摘要翻译： 本发明涉及半导体装置的保护装置。 本发明可以防止由于器件的小型化导致的栅极击穿电压的下降，而不会妨碍附接到其上的电路的高速性能。 本发明通过降低作为保护装置的主要部件的表面击穿型MOS晶体管的表面击穿电压并且降低击穿之后的电阻来提高可施加到器件的输入端子的电压。 这可以通过例如通过降低区域的深度等来增加其中配置MOS晶体管的区域的浓度来实现。

    Semiconductor integrated circuit
    2.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US4609835A

    公开(公告)日：1986-09-02

    申请号：US471130

    申请日：1983-03-01

    申请人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki

    发明人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki

    IPC分类号： G11C11/412 ,  H01L27/06 ,  H01L27/085 ,  H01L27/11 ,  G11C11/40 ,  H01L27/04 ,  H01L29/78 ,  H03K19/094

    CPC分类号： H01L27/0688 ,  G11C11/412 ,  H01L27/085 ,  H01L27/1104 ,  H01L27/1112

    摘要： Disclosed is a semiconductor integrated circuit which comprises an n-type silicon substrate, a p-type well region having an opening at a part thereof, which is formed on the surface portion of the substrate, an MOS transistor formed in the p-type region and a resistance layer extended from the drain region of the MOS transistor to the opening of the p-type well region through a insulating film formed on the surface of the substrate, in which the drain region of the MOS transistor is electrically connected to the silicon substrate through the resistance layer so that a current is supplied to the MOS transistor.

    摘要翻译： 公开了一种半导体集成电路，其包括n型硅衬底，形成在衬底的表面部分上的具有开口的p型阱区，形成在p型区域中的MOS晶体管 以及电阻层，其通过形成在所述衬底的表面上的绝缘膜从所述MOS晶体管的漏极区延伸到所述p型阱区的开口，其中所述MOS晶体管的漏极区域与所述硅 衬底通过电阻层，以便向MOS晶体管提供电流。

    Semiconductor memory with divided bit load and data bus lines
    3.
    发明授权
    Semiconductor memory with divided bit load and data bus lines 失效
    半导体存储器采用分割位负载和数据总线

    公开(公告)号：US5172335A

    公开(公告)日：1992-12-15

    申请号：US727314

    申请日：1991-07-01

    申请人： Toshio Sasaki ,  Osamu Minato ,  Shigeru Honjiyo ,  Koichiro Ishibashi ,  Toshiaki Masuhara

    发明人： Toshio Sasaki ,  Osamu Minato ,  Shigeru Honjiyo ,  Koichiro Ishibashi ,  Toshiaki Masuhara

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419

    摘要： A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified. A pair of driving amplifiers (34) further amplify each high and low output before applying them to an output data bus (38).

    摘要翻译： 静态RAM存储器被分成多个垫（12）。 每对垫子中的字线（16）由x解码器（14）访问。 列或位线由y解码器（20）访问，y解码器选择性地将成对的位线（22）连接到公共数据总线段（24）。 晶体管（60,62）在写入周期期间将选定的位线与负载连接，以稳定写入数据的位线和存储单元。 x解码器与近字线（16a）连接，用于寻址每个垫的近一半，并且与远程字线（16b）可操作地连接，用于寻址每个垫的远程一半中的字线。 以这种方式，每个垫子被分成两个有效的垫子。 实际的垫内的所有有效垫的位线与相同的输出数据总线段连接。 为每个存储器位提供一对感测放大器（32），该位被同时访问。 八位，使得每个触发器存储单元（18）的高和低输出都被放大。 一对驱动放大器（34）在将它们施加到输出数据总线（38）之前进一步放大每个高和低输出。

    Tri-state type driver circuit
    4.
    发明授权
    Tri-state type driver circuit 失效
    三态驱动电路

    公开(公告)号：US4280065A

    公开(公告)日：1981-07-21

    申请号：US969269

    申请日：1978-12-14

    申请人： Osamu Minato ,  Toshiaki Masuhara ,  Toshio Sasaki ,  Masaharu Kubo

    发明人： Osamu Minato ,  Toshiaki Masuhara ,  Toshio Sasaki ,  Masaharu Kubo

    IPC分类号： H03K19/0175 ,  H03K5/02 ,  H03K19/082 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/0948 ,  H03K3/01 ,  H03K19/08

    CPC分类号： H03K19/09429 ,  H03K19/0823 ,  H03K19/09448 ,  H03K5/023

    摘要： This invention relates to a tri-state type driver circuit in which any one of the three possible output signals of "float", "on", or "off" is produced at high speed even when an output terminal is accompanied with a great load. The tri-state type driver circuit comprises an output inverter circuit which employs a bipolar transistor as a load thereof and a MOS-FET as a driver thereof, a first logical circuit which is coupled to an input terminal of the bipolar transistor, which first logical circuit is made up of a C-MOS circuit receiving an external select signal and a C-MOS circuit having an input signal transmitted thereto and whose output can be specified by the external select signal, and a second logical circuit which is coupled to an input terminal of the MOS-FET, which second logical circuit is made up of a C-MOS circuit receiving the external select signal and a C-MOS circuit having the input signal transmitted thereto. The state of the external select signal will determine whether the driver circuit output will be "float" (regardless of the input to the driver circuit) or "on" or "off" (in correspondence with the input to the driver circuit).

    摘要翻译： 本发明涉及一种三态型驱动电路，其中即使输出端子伴随着大的负载，也可以高速度地产生“浮动”，“接通”或“断开”的三个可能的输出信号中的任何一个 。 三态型驱动器电路包括采用双极晶体管作为其负载的输出反相器电路和作为其驱动器的MOS-FET，耦合到双极晶体管的输入端的第一逻辑电路，第一逻辑 电路由接收外部选择信号的C-MOS电路和具有传输的输入信号的C-MOS电路组成，其输出可由外部选择信号指定，第二逻辑电路耦合到输入端 MOS-FET的端子，该第二逻辑电路由接收外部选择信号的C-MOS电路和传输了该输入信号的C-MOS电路组成。 外部选择信号的状态将决定驱动器电路输出是否为“浮动”（不管驱动电路的输入）还是“开”或“关”（与驱动电路的输入相对应）。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4261004A

    公开(公告)日：1981-04-07

    申请号：US929959

    申请日：1978-08-01

    申请人： Toshiaki Masuhara ,  Osamu Minato ,  Yoshio Sakai ,  Toshio Sasaki ,  Masaharu Kubo ,  Kotaro Nishimura ,  Tokumasa Yasui

    发明人： Toshiaki Masuhara ,  Osamu Minato ,  Yoshio Sakai ,  Toshio Sasaki ,  Masaharu Kubo ,  Kotaro Nishimura ,  Tokumasa Yasui

    IPC分类号： H03F1/52 ,  H01L21/02 ,  H01L21/822 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/78 ,  H03F1/42

    CPC分类号： H01L28/20 ,  H01L27/0251 ,  H01L27/0288

    摘要： On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K.OMEGA./.quadrature. and a second polycrystalline silicon member having a resistivity lower than 1 K.OMEGA./.quadrature. and being maintained at a fixed potential. This second polycrystalline silicon member faces at least a part of the first silicon member with polycrystalline silicon of a resistivity higher than 100 K.OMEGA./.quadrature. interposed therebetween. The input terminal of the first polycrystalline silicon member is connected to an input pad of the MOS type semiconductor device to be protected and the output terminal of the first polycrystalline silicon member is connected to an input gate of the semiconductor device to be protected. The input gate of the semiconductor device is protected by utilizing the punch-through effect in the interior of the polycrystalline silicon having a resistivity higher than 100 K.OMEGA./.quadrature..

    摘要翻译： 在形成有要形成有待保护的MOS型半导体器件的半导体衬底的表面上的绝缘膜的表面上形成有具有输入和输出端子的电阻率低于1KΩ的第一多晶硅元件， 并且具有电阻率低于1KΩ/□并且保持在固定电位的第二多晶硅部件。 该第二多晶硅部件面对第一硅部件的至少一部分，其中多晶硅的电阻率高于100KΩ，并插入其间。 第一多晶硅部件的输入端子连接到要被保护的MOS型半导体器件的输入焊盘，并且第一多晶硅部件的输出端子连接到待保护的半导体器件的输入栅极。 半导体器件的输入栅极通过利用电阻率高于100KΩ/□的多晶硅的内部的穿透效应来保护。

    Semiconductor memory with divided bit load and data bus lines
    6.
    发明授权
    Semiconductor memory with divided bit load and data bus lines 失效

    公开(公告)号：US4935901A

    公开(公告)日：1990-06-19

    申请号：US158259

    申请日：1988-02-19

    申请人： Toshio Sasaki ,  Osamu Minato ,  Shigeru Honjiyo ,  Koichiro Ishibashi ,  Toshiaki Masuhara

    发明人： Toshio Sasaki ,  Osamu Minato ,  Shigeru Honjiyo ,  Koichiro Ishibashi ,  Toshiaki Masuhara

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419

    摘要： A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified. A pair of driving amplifiers (34) further amplify each high and low output before applying them to an output data bus (38).

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4937790A

    公开(公告)日：1990-06-26

    申请号：US227893

    申请日：1988-08-03

    申请人： Toshio Sasaki ,  Toshiaki Masuhara ,  Osamu Minato

    发明人： Toshio Sasaki ,  Toshiaki Masuhara ,  Osamu Minato

    IPC分类号： G11C29/00

    CPC分类号： G11C29/76 ,  G11C29/808

    摘要： A semiconductor memory device is disclosed, in which a word line address translation unit, a data line address translation unit, a first spare memory and a second spare memory are provided in addition to a main memory to relieve a defective memory cell in the main memory. Spare word line address signals for selecting a spare word line on the first spare memory are written in the word line address translation unit, spare data line address signals for selecting a spare data line on the second spare memory are written in the data line address translation unit, and each of the word line address translation unit and the data line address translation unit is constructed of an ordinary semiconductor memory of the multi-bit output type.

    摘要翻译： 公开了一种半导体存储器件，其中除了主存储器之外还提供字线地址转换单元，数据线地址转换单元，第一备用存储器和第二备用存储器，以减轻主存储器中的有缺陷的存储器单元 。 用于选择第一备用存储器上的备用字线的备用字线地址信号被写入字线地址转换单元中，用于选择第二备用存储器上的备用数据线的备用数据线地址信号被写入数据线地址转换 单位，并且字线地址转换单元和数据线地址转换单元中的每一个由多位输出类型的普通半导体存储器构成。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4942556A

    公开(公告)日：1990-07-17

    申请号：US377181

    申请日：1989-07-10

    申请人： Toshio Sasaki ,  Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Toshiaki Masuhara

    发明人： Toshio Sasaki ,  Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Toshiaki Masuhara

    IPC分类号： G11C15/04 ,  G11C29/00 ,  G11C29/44

    CPC分类号： G11C29/76 ,  G11C15/04 ,  G11C15/046 ,  G11C29/44

    摘要： In a defect relieving technology which replaces defective memory cells of a semiconductor memory device by spare memory cells, use is made of an associative memory. Address information of a defective memory cell is stored as a reference data of the associative memory, and new address information of a spare memory cell is written down as output data of the associative memory. A variety of improvements are made to the associative memory. For instance, a plurality of coincidence detection signal lines of the associative memory are divided into at least two groups, and one group among them is selected by switching means. Reference data of the associative memory comprises three values consisting of binary information of "0" and "1", and don't care value "X". The associative memory further includes a plurality of electrically programable non-volatile semiconductor memory elements.

    摘要翻译： 在通过备用存储器单元代替半导体存储器件的缺陷存储单元的缺陷解除技术中，使用关联存储器。 存储有缺陷的存储单元的地址信息被存储为关联存储器的参考数据，并且备用存储单元的新地址信息被写入作为关联存储器的输出数据。 对联想记忆进行了各种改进。 例如，关联存储器的多个符合检测信号线被划分为至少两组，其中一组由切换装置选择。 关联存储器的参考数据包括由“0”和“1”的二进制信息组成的三个值，并且不关心值“X”。 关联存储器还包括多个可电可编程的非易失性半导体存储器元件。