公开(公告)号：US10670958B2

公开(公告)日：2020-06-02

申请号：US15937825

申请日：2018-03-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: G03F1/36 ,  G03F7/20 ,  H01L27/108

Abstract: A method of forming a layout pattern is disclosed. First, an array comprising a plurality of main features is provided wherein the main features are arranged into a plurality of rows along a first direction and are parallel and staggered along a second direction. Assistant features are inserted into each row of the main features. A shortest distance d1 between the main features in row n to the main features in row n+1 and a shortest distance d2 between the main feature in row n−1 to the main feature in row n+1 are obtained. The assistance features inserted in row n of the main features are then adjusted according to the difference between the distances d1 and d2. After that, the main features and the assistant features are output to a photo mask.

公开(公告)号：US20190341252A1

公开(公告)日：2019-11-07

申请号：US15968680

申请日：2018-05-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ming-Te Wei ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Chien-Ting Ho

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02

Abstract: A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.

公开(公告)号：US10396073B2

公开(公告)日：2019-08-27

申请号：US15610642

申请日：2017-06-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Chien-Ting Ho ,  Shih-Fang Tzou

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/108 ,  H01L21/8234

Abstract: A method for fabricating semiconductor device includes the steps of first forming a first trench and a second trench in a substrate and then forming a shallow trench isolation (STI) in the first trench, in which the STI comprises a top portion and a bottom portion and a top surface of the top portion is even with or higher than a bottom surface of the second trench. Next, a conductive layer is formed in the first trench and the second trench to form a first gate structure and a second gate structure.

公开(公告)号：US20190206874A1

公开(公告)日：2019-07-04

申请号：US16294934

申请日：2019-03-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.

公开(公告)号：US10199258B2

公开(公告)日：2019-02-05

申请号：US15384940

申请日：2016-12-20

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chieh-Te Chen ,  Hsien-Shih Chu ,  Ming-Feng Kuo ,  Fu-Che Lee ,  Chien-Ting Ho ,  Chiung-Lin Hsu ,  Feng-Yi Chang ,  Yi-Wang Zhan ,  Li-Chiang Chen ,  Chien-Cheng Tsai ,  Chin-Hsin Chiu

IPC: H01L21/762 ,  H01L21/308

Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.

公开(公告)号：US20180350817A1

公开(公告)日：2018-12-06

申请号：US16043166

申请日：2018-07-24

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho ,  Wen-Chieh Lu ,  Li-Wei Liu

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.

公开(公告)号：US20180335703A1

公开(公告)日：2018-11-22

申请号：US15937825

申请日：2018-03-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: G03F7/20 ,  G03F1/36 ,  G06F17/50

Abstract: A method of forming a layout pattern is disclosed. First, an array comprising a plurality of main features is provided wherein the main features are arranged into a plurality of rows along a first direction and are parallel and staggered along a second direction. Assistant features are inserted into each row of the main features. A shortest distance d1 between the main features in row n to the main features in row n+1 and a shortest distance d2 between the main feature in row n−1 to the main feature in row n+1 are obtained. The assistance features inserted in row n of the main features are then adjusted according to the difference between the distances d1 and d2. After that, the main features and the assistant features are output to a photo mask.

公开(公告)号：US20180308923A1

公开(公告)日：2018-10-25

申请号：US15927103

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L49/02 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L28/82 ,  H01L27/10808 ,  H01L27/10855 ,  H01L28/87 ,  H01L29/94

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

公开(公告)号：US20180226409A1

公开(公告)日：2018-08-09

申请号：US15884399

申请日：2018-01-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.

公开(公告)号：US20180197868A1

公开(公告)日：2018-07-12

申请号：US15866482

申请日：2018-01-10

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan ,  Yung-Ming Wang ,  Chien-Ting Ho

IPC: H01L27/108 ,  H01L21/76 ,  H01L21/02 ,  H01L21/3115

CPC classification number: H01L27/10891 ,  H01L21/02164 ,  H01L21/31155 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/76237

Abstract: A semiconductor device and a manufacturing method thereof include providing a substrate including an active region of a conductivity type and an isolation structure, in which the isolation structure surrounds the active region; forming a word line trench on the substrate, the word line trench intersecting the active region; and forming two doped regions in the active region at two sides of the word line trench respectively, in which each doped region and a bottom surface of the word line trench are located in a same level, and each doped region includes dopants of the conductivity type or an intrinsic semiconductor dopants.