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    Semiconductor Structure
    52.
    发明申请
    Semiconductor Structure 有权
    半导体结构

    公开(公告)号：US20160163797A1

    公开(公告)日：2016-06-09

    申请号：US14594159

    申请日：2015-01-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jiun Shen ,  Chia-Jong Liu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Man-Ling Lu ,  Yi-Wei Chen ,  Jhen-Cyuan Li

    IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847

    Abstract: The present invention provides a semiconductor structure, comprising a substrate, a gate structure, a source/drain region and at least a dislocation. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure. The dislocation is located in the source/drain region, and is asymmetrical relating to a middle axis of the source/drain region.

    Abstract translation: 本发明提供一种半导体结构，其包括衬底，栅极结构，源极/漏极区域和至少位错。 栅极结构设置在基板上。 源极/漏极区域在栅极结构的两侧设置在衬底中。 位错位于源极/漏极区域中，并且与源极/漏极区域的中间轴线不对称。

    Semiconductor device with epitaxial structure
    53.
    发明授权
    Semiconductor device with epitaxial structure 有权
    具有外延结构的半导体器件

    公开(公告)号：US09318609B2

    公开(公告)日：2016-04-19

    申请号：US14620209

    申请日：2015-02-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Cheng-Guo Chen ,  Chien-Ting Lin

    IPC: H01L27/01 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/161

    CPC classification number: H01L29/7851 ,  H01L21/8234 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7855

    Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

    Abstract translation: 半导体器件包括鳍结构，隔离结构，栅极结构和外延结构。 翅片结构从衬底的表面突出并且包括顶表面和两个侧壁。 隔离结构围绕翅片结构。 栅极结构覆盖鳍结构的一部分的顶表面和两个侧壁，并且覆盖隔离结构的一部分。 栅极结构下的隔离结构具有第一顶表面，并且栅极结构两侧的隔离结构具有第二顶表面。 第一顶面高于第二顶面。 外延层设置在栅极结构的一侧并与鳍结构直接接触。

    FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE
    55.
    发明申请
    FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE 有权
    半导体结构的制造方法

    公开(公告)号：US20150364568A1

    公开(公告)日：2015-12-17

    申请号：US14341838

    申请日：2014-07-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Man-Ling Lu ,  Chia-Jong Liu ,  Wen-Jiun Shen ,  Yi-Wei Chen

    IPC: H01L29/66

    CPC classification number: H01L29/6656 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

    Abstract: A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.

    Abstract translation: 半导体结构的制造方法包括以下步骤。 首先，在基板上设置栅极结构，在基板和栅极结构上形成第一材料层。 接下来，在栅极结构的两侧将硼掺杂剂注入到衬底中以形成第一掺杂区，并且在栅极结构的两侧将P型导电掺杂剂注入到衬底中，以形成第二掺杂区 地区。 如下，在第一材料层上形成第二材料层。 最后，栅极结构的两侧的第二材料层，第一材料层和衬底被顺序地蚀刻，并且在栅极结构的两侧在衬底中形成凹部，其中凹部位于 第一掺杂区域。

    Semiconductor process
    57.
    发明授权
    Semiconductor process 有权
    半导体工艺

    公开(公告)号：US09070710B2

    公开(公告)日：2015-06-30

    申请号：US13912218

    申请日：2013-06-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ssu-I Fu ,  Cheng-Guo Chen ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chien-Ting Lin

    IPC: H01L29/66

    CPC classification number: H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848

    Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess.

    Abstract translation: 半导体工艺包括以下步骤。 提供基板。 至少在基板上形成翅片状结构，形成与翅片状结构部分重叠的栅极结构。 随后，在衬底上覆盖地形成电介质层，除去电介质层的一部分，以在鳍状结构上形成第一间隔物，除了鳍状结构之外还形成第二间隔物。 此外，去除第二间隔件和鳍状结构的一部分以在栅极结构的一侧形成至少一个凹部，并且在凹部中形成外延层。

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