中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

66 records (took 0.053 seconds)

    Semiconductor structure and method for forming the same
    53.
    发明授权
    Semiconductor structure and method for forming the same 有权

    公开(公告)号：US11659772B2

    公开(公告)日：2023-05-23

    申请号：US17705404

    申请日：2022-03-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Rai-Min Huang

    IPC: H10N50/01 ,  H01L23/544 ,  H10B61/00 ,  H10N50/80

    CPC classification number: H10N50/01 ,  H01L23/544 ,  H10B61/00 ,  H10N50/80 ,  H01L2223/54426

    Abstract: A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.

    Semiconductor structure and method for forming the same
    56.
    发明授权
    Semiconductor structure and method for forming the same 有权

    公开(公告)号：US11322682B2

    公开(公告)日：2022-05-03

    申请号：US17152703

    申请日：2021-01-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Rai-Min Huang

    IPC: H01L43/12 ,  H01L23/544 ,  H01L43/02 ,  H01L27/22

    Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY
    57.
    发明申请
    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20210225933A1

    公开(公告)日：2021-07-22

    申请号：US16792271

    申请日：2020-02-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

    IPC: H01L27/22 ,  H01L23/528 ,  H01L43/02

    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region and a gate pattern extending from the first active region to the second active region, in which the gate pattern includes a H-shape according to a top view. Preferably, the gate pattern includes a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, and a third gate pattern connecting the first gate pattern and the second gate pattern along a second direction.

    Semiconductor device with magnetic tunnel junction
    58.
    发明申请
    Semiconductor device with magnetic tunnel junction 有权

    公开(公告)号：US20210028353A1

    公开(公告)日：2021-01-28

    申请号：US16554531

    申请日：2019-08-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Tsai ,  Rai-Min Huang

    IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02

    Abstract: A semiconductor device includes a substrate, an array of magnetic tunnel junctions (MTJs), an array of first dummy MTJs, and an array of second dummy MTJs. The substrate includes an array region defined thereon, and the array region includes at least an outermost corner. The array of MTJs is disposed in the array region. The array of the first dummy MTJs is disposed along the outermost corner of the array region. The array of the second dummy MTJs is disposed around the array region and the array of first dummy MTJs.

    Manufacturing method of patterned structure of semiconductor
    59.
    发明授权
    Manufacturing method of patterned structure of semiconductor 有权

    公开(公告)号：US10090398B2

    公开(公告)日：2018-10-02

    申请号：US15648439

    申请日：2017-07-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Rai-Min Huang ,  I-Ming Tseng ,  Tong-Jyun Huang ,  Kuan-Hsien Li

    IPC: H01L29/66 ,  H01L29/40 ,  H01L21/308 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

    Abstract: A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus.

Patent Agency Ranking