公开(公告)号：US11508904B2

公开(公告)日：2022-11-22

申请号：US17308057

申请日：2021-05-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L29/82 ,  G11C11/16 ,  H01L43/08 ,  G11C5/06 ,  H01L27/22

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.

公开(公告)号：US20220367791A1

公开(公告)日：2022-11-17

申请号：US17348776

申请日：2021-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Dong-Ming Wu ,  Chen-Yi Weng ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01L27/22 ,  H01F10/32

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

公开(公告)号：US20220310902A1

公开(公告)日：2022-09-29

申请号：US17242322

申请日：2021-04-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ching-Hua Hsu ,  Si-Han Tsai ,  Shun-Yu Huang ,  Chen-Yi Weng ,  Ju-Chun Fan ,  Che-Wei Chang ,  Yi-Yu Lin ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Ya-Jyuan Hung

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

公开(公告)号：US20220302369A1

公开(公告)日：2022-09-22

申请号：US17239667

申请日：2021-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Bo-Yun Huang ,  Wen-Wen Zhang ,  Kun-Chen Ho

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) structure is provided in the present invention, including multiple MRAM cells, and an atomic layer deposition dielectric layer between and at outer sides of the MRAM cells, wherein the material of top electrode layer is titanium nitride, and the nitrogen percentage is greater than titanium percentage and further greater than oxygen percentage in the titanium nitride, and the nitrogen percentage gradually increases inward from the top surface of top electrode layer to a depth and then start to gradually decrease to a first level and then remains constant, and the titanium percentage gradually decreases inward from the top surface of top electrode layer to the depth and then start to gradually increase to a second level and then remains constant.

公开(公告)号：US20220115584A1

公开(公告)日：2022-04-14

申请号：US17088531

申请日：2020-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

公开(公告)号：US20220115583A1

公开(公告)日：2022-04-14

申请号：US17082043

申请日：2020-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A semiconductor device includes a storage element on a substrate. The storage element has a tapered upper end structure. The tapered upper end structure includes a top electrode and a spacer surrounding the top electrode. A gap-fill dielectric layer is disposed around the spacer. A conductive cap layer covers the top electrode and the spacer. An inter-metal dielectric (IMD) layer is disposed on the conductive cap layer. A metal interconnection is disposed in the IMD layer and electrically connected to the top electrode through the conductive cap layer.

公开(公告)号：US20220059761A1

公开(公告)日：2022-02-24

申请号：US17516669

申请日：2021-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Chen-Yi Weng ,  Si-Han Tsai ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.

公开(公告)号：US20210343935A1

公开(公告)日：2021-11-04

申请号：US16884060

申请日：2020-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Wei Chen ,  Po-Kai Hsu ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/12 ,  H01L43/02 ,  H01F10/32

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

公开(公告)号：US20210328133A1

公开(公告)日：2021-10-21

申请号：US15930425

申请日：2020-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.

公开(公告)号：US11139428B2

公开(公告)日：2021-10-05

申请号：US16589083

申请日：2019-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Si-Han Tsai ,  Che-Wei Chang ,  Jing-Yin Jhang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.