公开(公告)号：US07592225B2

公开(公告)日：2009-09-22

申请号：US11623314

申请日：2007-01-15

申请人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

发明人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

摘要翻译： 提供了高密度半导体器件及其制造方法。 利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。 形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。 具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。 当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。 匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

公开(公告)号：US07495282B2

公开(公告)日：2009-02-24

申请号：US11626778

申请日：2007-01-24

申请人： Takashi Orimoto ,  James Kai ,  Henry Chien ,  George Matamis

发明人： Takashi Orimoto ,  James Kai ,  Henry Chien ,  George Matamis

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.

摘要翻译： 一系列非易失性存储单元通过源/漏区连接在一起，其包括在上层中由固定电荷产生的反型层。 控制栅极在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。 可以通过等离子体氮化形成固定电荷层。

公开(公告)号：US20080248622A1

公开(公告)日：2008-10-09

申请号：US12061641

申请日：2008-04-02

申请人： George Matamis ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  Tuan Pham

发明人： George Matamis ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  Tuan Pham

IPC分类号： H01L21/336

CPC分类号： H01L27/11543 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11541

摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the strips defines the dimension of the resulting charge storage structures in the column direction. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. Strips of control gate material are formed between strips of charge storage material adjacent in the column direction. The strips of charge storage and control gate material are divided along their lengths in the row direction as part of forming isolation trenches and columns of active areas. After dividing the strips, the charge storage material at the peripheral circuitry region of the substrate is etched to define a gate dimension in the column direction for a peripheral transistor. Control gate interconnects can be formed to connect together rows of isolated control gates to extrinsically form word lines.

摘要翻译： 提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成的外围电路形成形成其的方法。 形成沿着行方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。 形成条带限定了所得电荷存储结构在列方向上的尺寸。 在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。 控制栅极材料条形成在沿着列方向相邻的电荷存储材料的条带之间。 电荷存储和控制栅极材料条沿着它们在行方向上的长度被划分，作为形成隔离沟槽和有源区的列的一部分。 在分割条之后，蚀刻衬底的外围电路区域处的电荷存储材料，以便在外围晶体管的列方向上限定栅极尺寸。 可以形成控制栅极互连以将行隔离的控制栅极连接在一起，以外部地形成字线。

公开(公告)号：US20080170438A1

公开(公告)日：2008-07-17

申请号：US11626778

申请日：2007-01-24

申请人： Takashi Orimoto ,  James Kai ,  Henry Chien ,  George Matamis

发明人： Takashi Orimoto ,  James Kai ,  Henry Chien ,  George Matamis

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.

摘要翻译： 一系列非易失性存储单元通过源/漏区连接在一起，其包括在上层中由固定电荷产生的反型层。 控制栅极在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。 可以通过等离子体氮化形成固定电荷层。

公开(公告)号：US20080169567A1

公开(公告)日：2008-07-17

申请号：US11623315

申请日：2007-01-15

申请人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

发明人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

IPC分类号： H01L23/52

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

摘要翻译： 提供了高密度半导体器件及其制造方法。 利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。 形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。 具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。 当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。 匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

公开(公告)号：US20120153376A1

公开(公告)日：2012-06-21

申请号：US12974235

申请日：2010-12-21

申请人： Johann Alsmeier ,  Vinod Purayath ,  James Kai ,  George Matamis

发明人： Johann Alsmeier ,  Vinod Purayath ,  James Kai ,  George Matamis

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A NAND device including a source, a drain and a channel located between the source and drain. The NAND device also includes a plurality of floating gates located over the channel and a plurality of electrically conducting fins. Each of the plurality of electrically conducting fins is located over one of the plurality of floating gates. The plurality of electrically conducting fins include a material other than polysilicon. The NAND device also includes a plurality of control gates. Each of the plurality of control gates is located adjacent to each of the plurality of floating gates and each of the plurality of electrically conducting fins.

摘要翻译： 一种NAND器件，包括源极，漏极和位于源极和漏极之间的沟道。 NAND器件还包括位于通道上方的多个浮动栅极和多个导电鳍片。 多个导电翅片中的每一个位于多个浮动栅极之一上。 多个导电翅片包括多晶硅以外的材料。 NAND器件还包括多个控制栅极。 多个控制栅极中的每一个位于与多个浮动栅极和多个导电散热片中的每一个相邻的位置。

公开(公告)号：US20110186799A1

公开(公告)日：2011-08-04

申请号：US13020054

申请日：2011-02-03

申请人： James Kai ,  Henry Chien ,  George Matamis

发明人： James Kai ,  Henry Chien ,  George Matamis

IPC分类号： H01L29/04 ,  H01L21/16 ,  H01L23/52 ,  B82Y99/00

CPC分类号： B82Y10/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/149

摘要： A non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete conductive nano-features separated from each other by an insulating matrix, where the plurality of discrete nano-features are located in direct contact with the storage element, and a second electrode. An alternative non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete insulating nano-features separated from each other by a conductive matrix, where the plurality of discrete insulating nano-features are located in direct contact with the storage element, and a second electrode.

摘要翻译： 非易失性存储单元包括第一电极，操舵元件，与转向元件串联定位的存储元件，多个离散的导电纳米特征，通过绝缘矩阵彼此分离，其中多个离散的纳米 - 特征位于与存储元件直接接触的位置，以及第二电极。 替代的非易失性存储单元包括第一电极，转向元件，与转向元件串联的存储元件，多个分立的绝缘纳米特征，其通过导电矩阵彼此分离，其中多个分立的绝缘 纳米特征位于与存储元件直接接触的位置，以及第二电极。

公开(公告)号：US08455939B2

公开(公告)日：2013-06-04

申请号：US12974235

申请日：2010-12-21

申请人： Johann Alsmeier ,  Vinod Purayath ,  James Kai ,  George Matamis

发明人： Johann Alsmeier ,  Vinod Purayath ,  James Kai ,  George Matamis

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A NAND device including a source, a drain and a channel located between the source and drain. The NAND device also includes a plurality of floating gates located over the channel and a plurality of electrically conducting fins. Each of the plurality of electrically conducting fins is located over one of the plurality of floating gates. The plurality of electrically conducting fins include a material other than polysilicon. The NAND device also includes a plurality of control gates. Each of the plurality of control gates is located adjacent to each of the plurality of floating gates and each of the plurality of electrically conducting fins.

摘要翻译： 一种NAND器件，包括源极，漏极和位于源极和漏极之间的沟道。 NAND器件还包括位于通道上方的多个浮动栅极和多个导电鳍片。 多个导电翅片中的每一个位于多个浮动栅极之一上。 多个导电翅片包括多晶硅以外的材料。 NAND器件还包括多个控制栅极。 多个控制栅极中的每一个位于与多个浮动栅极和多个导电散热片中的每一个相邻的位置。

公开(公告)号：US08737111B2

公开(公告)日：2014-05-27

申请号：US13157191

申请日：2011-06-09

申请人： Franz Kreupl ,  Xiying Costa ,  James Kai ,  Raghuveer S. Makala

发明人： Franz Kreupl ,  Xiying Costa ,  James Kai ,  Raghuveer S. Makala

IPC分类号： G11C11/00

CPC分类号： H01L27/2409 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。 第一和第二电阻切换层都可以具有双极或单极开关特性。 在存储单元的置位或复位操作中，跨越第一和第二电极施加电场。 离子电流在电阻切换层中流动，有助于切换机构。 由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。 提供了用于RSME不同层的材料和材料的组合。

公开(公告)号：US20110310655A1

公开(公告)日：2011-12-22

申请号：US13157204

申请日：2011-06-09

申请人： Franz Kreupl ,  Abhijit Bandyopadhyay ,  Yung-Tin Chen ,  Chu-Chen Fu ,  Wipul Pemsiri Jayasekara ,  James Kai ,  Raghuveer S Makala ,  Peter Rabkin ,  George Samachisa ,  Jingyan Zhang

发明人： Franz Kreupl ,  Abhijit Bandyopadhyay ,  Yung-Tin Chen ,  Chu-Chen Fu ,  Wipul Pemsiri Jayasekara ,  James Kai ,  Raghuveer S Makala ,  Peter Rabkin ,  George Samachisa ,  Jingyan Zhang

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L27/2409 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。 第一和第二电阻切换层都可以具有双极或单极开关特性。 在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。 由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。 提供了用于RSME不同层的材料和材料的组合。