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51.发明授权Methods of forming spacer patterns using assist layer for high density semiconductor devices 有权使用辅助层形成间隔图案的方法用于高密度半导体器件公开(公告)号：US07592225B2
公开(公告)日：2009-09-22
申请号：US11623314
申请日：2007-01-15
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/32139 , H01L21/0337 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译： 提供了高密度半导体器件及其制造方法。 利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。 形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。 具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。 当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。 匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。
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52.发明申请Methods Of Fabricating Non-Volatile Memory With Integrated Peripheral Circuitry And Pre-Isolation Memory Cell Formation 有权使用集成外围电路和预隔离存储器单元形成的非易失性存储器的制造方法公开(公告)号：US20080248622A1
公开(公告)日：2008-10-09
申请号：US12061641
申请日：2008-04-02
申请人： George Matamis , Takashi Orimoto , Masaaki Higashitani , James Kai , Tuan Pham
发明人： George Matamis , Takashi Orimoto , Masaaki Higashitani , James Kai , Tuan Pham
IPC分类号： H01L21/336
CPC分类号： H01L27/11543 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11541
摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the strips defines the dimension of the resulting charge storage structures in the column direction. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. Strips of control gate material are formed between strips of charge storage material adjacent in the column direction. The strips of charge storage and control gate material are divided along their lengths in the row direction as part of forming isolation trenches and columns of active areas. After dividing the strips, the charge storage material at the peripheral circuitry region of the substrate is etched to define a gate dimension in the column direction for a peripheral transistor. Control gate interconnects can be formed to connect together rows of isolated control gates to extrinsically form word lines.
摘要翻译： 提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成的外围电路形成形成其的方法。 形成沿着行方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。 形成条带限定了所得电荷存储结构在列方向上的尺寸。 在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。 控制栅极材料条形成在沿着列方向相邻的电荷存储材料的条带之间。 电荷存储和控制栅极材料条沿着它们在行方向上的长度被划分，作为形成隔离沟槽和有源区的列的一部分。 在分割条之后，蚀刻衬底的外围电路区域处的电荷存储材料，以便在外围晶体管的列方向上限定栅极尺寸。 可以形成控制栅极互连以将行隔离的控制栅极连接在一起，以外部地形成字线。
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53.发明申请公开(公告)号：US20080169567A1
公开(公告)日：2008-07-17
申请号：US11623315
申请日：2007-01-15
IPC分类号： H01L23/52
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译： 提供了高密度半导体器件及其制造方法。 利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。 形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。 具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。 当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。 匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。
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公开(公告)号：US20080142874A1
公开(公告)日：2008-06-19
申请号：US11611860
申请日：2006-12-16
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Hidehiko Shiraiwa , Takayuki Maruyama , Kuo-Tung Chang , YouSeok Suh , Amol Ramesh Joshi , Harpreet Sachar , Simon Siu-Sing Chan
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Hidehiko Shiraiwa , Takayuki Maruyama , Kuo-Tung Chang , YouSeok Suh , Amol Ramesh Joshi , Harpreet Sachar , Simon Siu-Sing Chan
IPC分类号： H01L29/792 , H01L21/3205
CPC分类号： H01L29/792 , H01L29/66833
摘要： A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.
摘要翻译： 提供一种用于形成集成电路系统的方法，包括：形成衬底; 在衬底上形成堆叠，所述堆叠具有侧壁并由电荷陷阱层和半导体层形成; 以及缝隙平面天线，用于氧化该叠层以形成具有沿该侧壁的保护层的保护罩。
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55.发明申请公开(公告)号：US20080079061A1
公开(公告)日：2008-04-03
申请号：US11529166
申请日：2006-09-28
申请人： Meng Ding , Amol Joshi , Takashi Orimoto , Jayendra Bhakta , Lei Xue , Satoshi Torii , Robert Bertram Ogle
发明人： Meng Ding , Amol Joshi , Takashi Orimoto , Jayendra Bhakta , Lei Xue , Satoshi Torii , Robert Bertram Ogle
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/4234
摘要： According to one exemplary embodiment, a structure, for example a flash memory cell, comprises a transistor gate dielectric stack situated on a semiconductor substrate. The transistor gate dielectric stack includes a bottom oxide layer, a silicon-rich nitride layer situated on the bottom oxide layer, a low silicon-rich nitride layer situated on the silicon-rich nitride layer, and a top oxide layer situated on the low silicon-rich nitride layer. This embodiment results in a nitride based flash memory cell having improved program speed and retention while maintaining a high erase speed. In another embodiment, a flash memory cell may further comprise a high-K dielectric layer situated on the transistor gate dielectric stack.
摘要翻译： 根据一个示例性实施例，诸如闪存单元的结构包括位于半导体衬底上的晶体管栅极电介质堆叠。 晶体管栅极电介质堆叠包括底部氧化物层，位于底部氧化物层上的富含硅的氮化物层，位于富硅氮化物层上的低富硅氮化物层和位于低硅上的顶部氧化物层 富含氮化物层。 该实施例导致基于氮化物的闪存单元具有改善的编程速度和保持，同时保持高的擦除速度。 在另一个实施例中，快闪存储器单元还可以包括位于晶体管栅极电介质叠层上的高K电介质层。
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56.发明申请公开(公告)号：US20050125133A1
公开(公告)日：2005-06-09
申请号：US10979164
申请日：2004-11-03
申请人： Noritaka Yamada , Takashi Orimoto
发明人： Noritaka Yamada , Takashi Orimoto
CPC分类号： B60T7/122 , B60T8/4872
摘要： A vehicle braking force control apparatus detects a period of time from when a braking force of a brake device is cancelled until a vehicle body speed in the backwards direction of a vehicle on a hill reaches a predetermined state, determines a brake output according to the detected period of time, and controls braking pressure according to the determined brake output. The period of time depends on the gradient of the hill. Therefore, by determining the brake output according to this period of time, braking force control according to the gradient of the hill is made possible even at an extremely slow speed at which the vehicle speed is undetectable.
摘要翻译： 车辆制动力控制装置检测从制动装置的制动力被取消直到车辆在山丘的后方的车身速度达到预定状态的时间段，根据检测到的制动器输出 并根据确定的制动输出控制制动压力。 这段时间取决于山坡的坡度。 因此，通过根据该时间段确定制动输出，即使在车速不可检测的极低速度下，也可以根据山坡的坡度进行制动力控制。
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公开(公告)号：US4618146A
公开(公告)日：1986-10-21
申请号：US643813
申请日：1984-08-23
申请人： Junichi Yoshida , Takashi Orimoto
发明人： Junichi Yoshida , Takashi Orimoto
CPC分类号： A63F13/843 , A63F13/02 , A63F13/24
摘要： In a video game apparatus, a first joystick and a second joystick each contain a stick, a game start key and a mode select key. A control circuit controls the video game apparatus in the following manner. In a one-player mode as selected, only the output signal from the joystick whose start key is operated, is supplied to the main frame of the video game apparatus. In a two-player mode as selected, the output signal from the joystick whose start key is operated is supplied to the main frame. In turn, a game is started. With the progression of the game, the output signals from the first and second joysticks are alternately applied to the main frame.
摘要翻译： 在视频游戏装置中，第一操纵杆和第二操纵杆各自包含棒，游戏开始键和模式选择键。 控制电路以下列方式控制视频游戏装置。 在所选择的单人模式中，只有来自操作起动键的操纵杆的输出信号被提供给视频游戏装置的主框架。 在选择的双人模式中，操作起动键的操纵杆的输出信号被提供给主框架。 反过来，游戏开始了。 随着游戏的进行，来自第一和第二操纵杆的输出信号被交替地施加到主框架。
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公开(公告)号：US08143661B2
公开(公告)日：2012-03-27
申请号：US11539984
申请日：2006-10-10
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要： A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.
摘要翻译： 提供一种存储单元系统，包括半导体衬底上的第一绝缘体层，第一绝缘体层上的电荷陷阱层和电荷陷阱层包括具有生长特性的第二绝缘体层的槽。
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59.发明授权公开(公告)号：US07444221B2
公开(公告)日：2008-10-28
申请号：US10979164
申请日：2004-11-03
申请人： Noritaka Yamada , Takashi Orimoto
发明人： Noritaka Yamada , Takashi Orimoto
IPC分类号： G06F7/70
CPC分类号： B60T7/122 , B60T8/4872
摘要： A vehicle braking force control apparatus detects a period of time from when a braking force of a brake device is cancelled until a vehicle body speed in the backwards direction of a vehicle on a hill reaches a predetermined state, determines a brake output according to the detected period of time, and controls braking pressure according to the determined brake output. The period of time depends on the gradient of the hill. Therefore, by determining the brake output according to this period of time, braking force control according to the gradient of the hill is made possible even at an extremely slow speed at which the vehicle speed is undetectable.
摘要翻译： 车辆制动力控制装置检测从制动装置的制动力被取消直到车辆在山丘的后方的车身速度达到预定状态的时间段，根据检测到的制动器输出 并根据确定的制动输出控制制动压力。 这段时间取决于山坡的坡度。 因此，通过根据该时间段确定制动输出，即使在车速不可检测的极低速度下，也可以根据山坡的坡度进行制动力控制。
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60.发明授权Memory cell having combination raised source and drain and method of fabricating same 有权具有组合升高源极和漏极的存储单元及其制造方法公开(公告)号：US07414277B1
公开(公告)日：2008-08-19
申请号：US11112884
申请日：2005-04-22
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of raised bitlines, where the bitlines have a lower portion formed by a first process and an upper portion formed by a second process.
摘要翻译： 提供了存储器件和制造方法。 存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。 栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。 存储装置包括一对升高的位线，其中位线具有由第一工艺形成的下部分和由第二工序形成的上部部分。
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