公开(公告)号：US20140063913A1

公开(公告)日：2014-03-06

申请号：US13985435

申请日：2012-12-17

Applicant: Yoshio Kawashima ,  Yukio Hayakawa

Inventor： Yoshio Kawashima ,  Yukio Hayakawa

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0064 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/56 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a variable resistance element and a first current steering element; and a current steering element parameter generation circuit. The current steering element parameter generation circuit includes: a third line placed between a substrate and a second interlayer dielectric; a fourth line placed above the second interlayer dielectric; and a second current steering element which is connected between the third line and the fourth line without the variable resistance element being interposed therebetween when the variable resistance element is removed between the third line and the fourth line and has the same non-linear current steering characteristics as the first current steering element.

Abstract translation: 非易失性存储器件包括：存储单元阵列，包括多个存储单元，每个存储单元包括可变电阻元件和第一电流控制元件; 和当前的导向元件参数产生电路。 当前的导向元件参数产生电路包括：放置在基板和第二层间电介质之间的第三线; 放置在第二层间电介质上方的第四线; 以及当在第三线和第四线之间移除可变电阻元件时，连接在第三线和第四线之间的第二电流导向元件，而不存在可变电阻元件，并具有相同的非线性电流转向特性 作为第一当前的转向元件。

公开(公告)号：US08618526B2

公开(公告)日：2013-12-31

申请号：US13501228

申请日：2011-08-11

Applicant: Haruyuki Sorada ,  Takeki Ninomiya ,  Takumi Mikawa ,  Yukio Hayakawa

Inventor： Haruyuki Sorada ,  Takeki Ninomiya ,  Takumi Mikawa ,  Yukio Hayakawa

IPC: H01L47/00

CPC classification number: H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675

Abstract: Provided are a nonvolatile memory device which can suppress non-uniformity in initial breakdown voltages among nonvolatile memory elements and prevent reduction of yield, and a manufacturing method thereof. The nonvolatile memory device includes a nonvolatile memory element (108) having a stacked-layer structure in which a resistance variable layer (106) is parallel to a main surface of a substrate (117) and is planarized, and a plug (103) electrically connected to either a first electrode (105) or a second electrode (107), and an area of an end surface of a plug (103) at which the plug (103) and the nonvolatile memory element (108) are connected together, the end surface being parallel to the main surface of the substrate (117), is greater than a cross-sectional area of a cross-section of a first transition metal oxide layer (115) which is an electrically-conductive region, the cross-section being parallel to the main surface of the substrate (117).

Abstract translation: 提供一种能够抑制非易失性存储元件之间的初始击穿电压的不均匀性并且防止产量降低的非易失性存储器件及其制造方法。 非易失性存储器件包括具有堆叠层结构的非易失性存储元件（108），其中电阻变化层（106）平行于衬底（117）的主表面并被平坦化;以及电极（103） 连接到第一电极（105）或第二电极（107），以及插头（103）的端面（103）的与插头（103）和非易失性存储元件（108）连接在一起的区域， 平行于基板（117）的主表面的端面大于作为导电区域的第一过渡金属氧化物层（115）的截面的横截面积，横截面 平行于基板（117）的主表面。

公开(公告)号：US08574957B2

公开(公告)日：2013-11-05

申请号：US13502769

申请日：2011-11-10

Applicant: Takumi Mikawa ,  Yukio Hayakawa ,  Takeki Ninomiya ,  Yoshio Kawashima

Inventor： Takumi Mikawa ,  Yukio Hayakawa ,  Takeki Ninomiya ,  Yoshio Kawashima

IPC: H01L21/00

CPC classification number: H01L27/101 ,  G11C13/0007 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

Abstract: An object of the present invention is to provide a method for manufacturing a variable resistance nonvolatile semiconductor memory element which can operate at a low voltage and high speed when initial breakdown is caused, and inhibit oxidization of a contact plug. The method for manufacturing the variable resistance nonvolatile semiconductor memory element, which includes a bottom electrode, a variable resistance layer, and a top electrode which are formed above a contact plug, includes oxidizing to insulate an end portion of the variable resistance layer prior to forming a bottom electrode by patterning a first conductive film.

Abstract translation: 本发明的目的是提供一种用于制造可变电阻非易失性半导体存储元件的方法，其可以在初始击穿时能够以低电压和高速工作，并且抑制接触插塞的氧化。 制造可变电阻型非易失性半导体存储元件的方法，其包括形成在接触插塞上方的底电极，可变电阻层和顶电极，包括在形成之前进行氧化以使可变电阻层的端部绝缘 通过图案化第一导电膜来形成底部电极。

公开(公告)号：US20130112935A1

公开(公告)日：2013-05-09

申请号：US13810245

申请日：2011-11-30

Applicant: Atsushi Himeno ,  Haruyuki Sorada ,  Yukio Hayakawa ,  Takumi Mikawa

Inventor： Atsushi Himeno ,  Haruyuki Sorada ,  Yukio Hayakawa ,  Takumi Mikawa

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/101 ,  H01L27/1052 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1675

Abstract: A nonvolatile memory element according to the present invention includes a first metal line; a plug formed on the first metal line and connected to the first metal line; a stacked structure including a first electrode, a second electrode, and a variable resistance layer, the stacked structure being formed on a plug which is connected to the first electrode; a second metal line formed on the stacked structure and directly connected to the second electrode; and a side wall protective layer which covers the side wall of the stacked structure and has an insulating property and an oxygen barrier property, wherein part of a lower surface of the second metal line is located under an upper surface of the stacked structure.

Abstract translation: 根据本发明的非易失性存储元件包括第一金属线; 形成在所述第一金属线上并连接到所述第一金属线的插头; 包括第一电极，第二电极和可变电阻层的堆叠结构，所述堆叠结构形成在连接到所述第一电极的插头上; 形成在所述堆叠结构上并直接连接到所述第二电极的第二金属线; 以及侧壁保护层，其覆盖层叠结构的侧壁，并且具有绝缘性和氧阻隔性，其中第二金属线的下表面的一部分位于堆叠结构的上表面的下方。

公开(公告)号：US08437173B2

公开(公告)日：2013-05-07

申请号：US13320654

申请日：2011-03-16

Applicant: Yukio Hayakawa ,  Takumi Mikawa ,  Yoshio Kawashima ,  Takeki Ninomiya

Inventor： Yukio Hayakawa ,  Takumi Mikawa ,  Yoshio Kawashima ,  Takeki Ninomiya

IPC: G11C11/00

CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

Abstract: A nonvolatile memory element which can be initialized at low voltage includes a variable resistance layer (116) located between a lower electrode (105) and an upper electrode (107) and having a resistance value that reversibly changes based on electrical signals applied between these electrodes. The variable resistance layer (116) includes at least two layers: a first variable resistance layer (1161) including a first transition metal oxide (116b); and a second variable resistance layer (1162) including a second transition metal oxide (116a) and a third transition metal oxide (116c). The second transition metal oxide (116a) has an oxygen deficiency higher than either oxygen deficiency of the first transition metal oxide (116b) or the third transition metal oxide (116c), and the second transition metal oxide (116a) and the third transition metal oxide (116c) are in contact with the first variable resistance layer (1161).

Abstract translation: 可以以低电压初始化的非易失性存储元件包括位于下电极（105）和上电极（107）之间的可变电阻层（116），并且具有基于施加在这些电极之间的电信号而可逆地改变的电阻值 。 可变电阻层（116）包括至少两层：包括第一过渡金属氧化物（116b）的第一可变电阻层（1161）; 和包括第二过渡金属氧化物（116a）和第三过渡金属氧化物（116c）的第二可变电阻层（1162）。 第二过渡金属氧化物（116a）的缺氧高于第一过渡金属氧化物（116b）或第三过渡金属氧化物（116c）的氧缺乏，第二过渡金属氧化物（116a）和第三过渡金属 氧化物（116c）与第一可变电阻层（1161）接触。

公开(公告)号：US20130015423A1

公开(公告)日：2013-01-17

申请号：US13637465

申请日：2011-11-18

Applicant: Takumi Mikawa ,  Yukio Hayakawa ,  Yoshio Kawashima ,  Takeki Ninomiya

Inventor： Takumi Mikawa ,  Yukio Hayakawa ,  Yoshio Kawashima ,  Takeki Ninomiya

IPC: H01L45/00 ,  H01L21/8239

CPC classification number: H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1675

Abstract: Provided is a method for manufacturing a variable resistance nonvolatile semiconductor memory element, and a nonvolatile semiconductor memory element which make it possible to operate at a low voltage and high speed when initial breakdown is caused, and exhibit favorable diode element characteristics. The method for manufacturing the nonvolatile semiconductor memory element includes, after forming a top electrode of a variable resistance element and at least before forming a top electrode of an MSM diode element, oxidizing to insulate a portion of a variable resistance film in a region around an end face of a variable resistance layer.

Abstract translation: 提供一种用于制造可变电阻非易失性半导体存储元件的方法，以及使得可以在初始击穿时以低电压和高速操作的可变电阻非易失性半导体存储元件，并且表现出良好的二极管元件特性。 制造非易失性半导体存储元件的方法包括：在形成可变电阻元件的顶部电极之后，并且至少在形成MSM二极管元件的顶部电极之前，氧化以使可变电阻膜的一部分在一个周围的区域中绝缘 可变电阻层的端面。

公开(公告)号：US20120326113A1

公开(公告)日：2012-12-27

申请号：US13582370

申请日：2011-06-09

Applicant: Shinichi Yoneda ,  Takumi Mikawa ,  Yukio Hayakawa ,  Takeki Ninomiya

Inventor： Shinichi Yoneda ,  Takumi Mikawa ,  Yukio Hayakawa ,  Takeki Ninomiya

IPC: H01L45/00

CPC classification number: H01L45/08 ,  G11C13/0007 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1625

Abstract: Provided are a non-volatile memory element which can reduce a voltage of an electric pulse required for initial breakdown, and can lessen non-uniformity of a resistance value of the non-volatile memory element, and a non-volatile memory device including the non-volatile memory element. A non-volatile memory element comprises a first electrode (103); a second electrode (105); and a variable resistance layer (104) interposed between the first electrode (103) and the second electrode (105), a resistance value of the variable resistance layer being changeable reversibly in response to an electric signal applied between the first electrode (103) and the second electrode (105); wherein the variable resistance layer (104) includes a first region (106) which is in contact with the first electrode (103) and comprises an oxygen-deficient transition metal oxide and a second region (107) which is in contact with the second electrode (105) and comprises a transition metal oxide having a smaller degree of oxygen deficiency than the first region (106); and wherein the second electrode (105) comprises an alloy including iridium and at least one precious metal having lower Young's modulus than iridium, and a content of iridium is not less than 50 atm %.

Abstract translation: 提供了一种非易失性存储元件，其可以降低初始击穿所需的电脉冲的电压，并且可以减小非易失性存储元件的电阻值的不均匀性，以及包括非易失性存储元件的非易失性存储器件， 非易失存储元件。 非易失性存储元件包括第一电极（103）; 第二电极（105）; 以及插入在第一电极（103）和第二电极（105）之间的可变电阻层（104），可变电阻层的电阻值响应于施加在第一电极（103）和 第二电极（105）; 其特征在于，所述可变电阻层（104）包括与所述第一电极（103）接触并且包含缺氧过渡金属氧化物的第一区域（106）和与所述第二电极（103）接触的第二区域 （105），并且包含与第一区域（106）相比氧缺乏程度较小的过渡金属氧化物; 并且其中所述第二电极（105）包括包含铱和至少一种具有比铱低的杨氏模量的贵金属的合金，并且铱的含量不小于50atm％。

公开(公告)号：US20120252184A1

公开(公告)日：2012-10-04

申请号：US13515761

申请日：2010-12-14

Applicant: Takeki Ninomiya ,  Yoshio Kawashima ,  Yukio Hayakawa ,  Takumi Mikawa

Inventor： Takeki Ninomiya ,  Yoshio Kawashima ,  Yukio Hayakawa ,  Takumi Mikawa

IPC: H01L21/8239

CPC classification number: C23C26/00 ,  C23C28/00 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: A variable resistance element comprises, when M is a transition metal element, O is oxygen, and x and y are positive numbers satisfying y>x; a lower electrode; a first oxide layer formed on the lower electrode and comprising MOx when a content ratio of O with respect to M is x; a second oxide layer formed on the first oxide layer and comprising MOy when a content ratio of O with respect to M is y; an upper electrode formed on the second oxide layer; a protective layer formed on the upper electrode and comprising an electrically conductive material having a composition different from a composition of the upper electrode; an interlayer insulating layer formed to cover the protective layer; and an upper contact plug formed inside an upper contact hole penetrating the interlayer insulating layer.

Abstract translation: 可变电阻元件包括当M是过渡金属元素时，O是氧，x和y是满足y> x的正数; 下电极 当相对于M的含量比为O时，形成在下电极上并包含MOx的第一氧化物层; 当相对于M的含量比为O时，形成在第一氧化物层上并包含MOy的第二氧化物层; 形成在所述第二氧化物层上的上电极; 形成在上电极上并具有不同于上电极的组成的组成的导电材料的保护层; 形成为覆盖保护层的层间绝缘层; 以及形成在贯穿层间绝缘层的上接触孔内部的上接触插塞。

公开(公告)号：US20120238055A1

公开(公告)日：2012-09-20

申请号：US13502769

申请日：2011-11-10

Applicant: Takumi Mikawa ,  Yukio Hayakawa ,  Takeki Ninomiya ,  Yoshio Kawashima

Inventor： Takumi Mikawa ,  Yukio Hayakawa ,  Takeki Ninomiya ,  Yoshio Kawashima

IPC: H01L21/02

CPC classification number: H01L27/101 ,  G11C13/0007 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

Abstract: An object of the present invention is to provide a method for manufacturing a variable resistance nonvolatile semiconductor memory element which can operate at a low voltage and high speed when initial breakdown is caused, and inhibit oxidization of a contact plug. The method for manufacturing the variable resistance nonvolatile semiconductor memory element, which includes a bottom electrode, a variable resistance layer, and a top electrode which are formed above a contact plug, includes oxidizing to insulate an end portion of the variable resistance layer prior to forming a bottom electrode by patterning a first conductive film.

Abstract translation: 本发明的目的是提供一种用于制造可变电阻非易失性半导体存储元件的方法，其可以在初始击穿时能够以低电压和高速工作，并且抑制接触插塞的氧化。 制造可变电阻型非易失性半导体存储元件的方法，其包括形成在接触插塞上方的底电极，可变电阻层和顶电极，包括在形成之前进行氧化以使可变电阻层的端部绝缘 通过图案化第一导电膜来形成底部电极。

公开(公告)号：US08264029B2

公开(公告)日：2012-09-11

申请号：US12002728

申请日：2007-12-17

Applicant: Yukio Hayakawa ,  Hiroyuki Nansei

Inventor： Yukio Hayakawa ,  Hiroyuki Nansei

IPC: H01L29/792 ,  H01L27/148 ,  H01L21/70 ,  H01L27/108 ,  H01L29/94 ,  H01L29/02 ,  H01L21/339

CPC classification number: H01L27/11517 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L23/5283 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66757 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.

Abstract translation: 本发明提供一种半导体器件，其位线之间的距离较短，并且容易实现更高的存储容量和密度，以及制造这种半导体器件的方法。 半导体器件包括：形成在衬底上的第一位线; 绝缘层，设置在所述基板上的所述第一位线之间，并且具有比所述第一位线更高的上表面; 沟道层，其设置在绝缘层的两个侧面上，并且耦合到相应的第一位线; 并且从形成有绝缘层的侧面向沟道层的相对侧面设置电荷存储层。