公开(公告)号：US20090103368A1

公开(公告)日：2009-04-23

申请号：US12339153

申请日：2008-12-19

申请人： Mikio OGAWA ,  Norihiro Fujita ,  Hiroshi Nakamura

发明人： Mikio OGAWA ,  Norihiro Fujita ,  Hiroshi Nakamura

IPC分类号： G11C11/34 ,  H01L29/788

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28

摘要： A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.

摘要翻译： 半导体存储器件包括存储单元阵列和读出放大器电路。 存储单元阵列包括连接到存储器单元的位线，该存储器单元可操作以存储第一逻辑数据和小区电流中比第一逻辑小的第二逻辑数据。 感测放大器电路具有用于钳位位线电压的钳位晶体管。 感测放大器电路用于通过钳位晶体管和位线检测所选存储单元中的数据。 当将控制电压施加到钳位晶体管的栅极时，感测放大器电路用于在至少两个第一和第二读取周期中从所选存储单元读取数据。 在第一和第二读取周期中，不同的控制电压施加到钳位晶体管的栅极。

公开(公告)号：US20090067847A1

公开(公告)日：2009-03-12

申请号：US11887279

申请日：2006-03-06

申请人： Hiroshi Nakamura

发明人： Hiroshi Nakamura

IPC分类号： H04B10/00

CPC分类号： G08C23/04 ,  G08C2201/32

摘要： A quick selection of a depression key provided with a remote controller is impeded, so that controllable characteristics of the remote controller are deteriorated, and a lifetime of a cell provided on the side of the remote controller is reduced in order to acquire transport motional information.While a remote control system is equipped with the remote controller and an infrared communication apparatus 33, a pattern for reflecting diffraction light by illumination light is provided with the remote controller, whereas a transmitting/receiving unit 37 and a control unit 39 are provided with the infrared communication apparatus 33. A light emitting unit 11 for emitting light to the pattern, and a light receiving unit 17 for receiving reflection light from the pattern are provided with the transmitting/receiving unit 37. A detecting unit 41 for detecting intensity of the light received by the light receiving unit 17, a calculating unit 43 for binary-processing the intensity of the detected light to obtain binary information in response to the intensity of the detected light, and a converting unit 45 for converting the binary information into a control signal for a main appliance are provided with the control unit 39.

摘要翻译： 阻碍了设置有遥控器的按键的快速选择，使得遥控器的可控特性恶化，并且减小了设置在遥控器一侧的单元的寿命以便获取传送运动信息。 在远程控制系统配备有遥控器和红外线通信装置33的情况下，遥控器设置有用于通过照明光反射衍射光的图案，而发送/接收单元37和控制单元39设置有 红外通信设备33.用于向该图案发射光的发光单元11和用于从该图案接收反射光的光接收单元17设置有发送/接收单元37.用于检测光的强度的检测单元41 由光接收单元17接收的计算单元43，用于响应于检测到的光的强度二次处理检测到的光的强度以获得二进制信息的计算单元43和用于将二进制信息转换为控制信号的转换单元45 主设备设置有控制单元39。

公开(公告)号：US07486569B2

公开(公告)日：2009-02-03

申请号：US11609646

申请日：2006-12-12

申请人： Norihiro Fujita ,  Hiroyuki Nagashima ,  Hiroshi Nakamura

发明人： Norihiro Fujita ,  Hiroyuki Nagashima ,  Hiroshi Nakamura

IPC分类号： G11C7/10

CPC分类号： G11C16/10

摘要： A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.

摘要翻译： 非易失性半导体存储器包括：第一半导体芯片，其上安装有第一存储器; 安装有第二存储器的第二半导体芯片; 其中，在作为复制目的地的第二存储器中，在启动将读取使能操作识别为可启用操作的命令之后执行读取使能操作，以及作为第一存储器的源的第一存储器的数据 复制，被复制到第二个内存。

公开(公告)号：US07486562B2

公开(公告)日：2009-02-03

申请号：US11194608

申请日：2005-08-02

申请人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

发明人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

IPC分类号： G11C11/34

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28

摘要： A semiconductor memory device comprises a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.

摘要翻译： 半导体存储器件包括存储单元阵列和读出放大器电路。 存储单元阵列包括连接到存储器单元的位线，该存储器单元可操作以存储第一逻辑数据和小区电流中比第一逻辑小的第二逻辑数据。 感测放大器电路具有用于钳位位线电压的钳位晶体管。 感测放大器电路用于通过钳位晶体管和位线检测所选存储单元中的数据。 当将控制电压施加到钳位晶体管的栅极时，感测放大器电路用于在至少两个第一和第二读取周期中从所选存储单元读取数据。 在第一和第二读取周期中，不同的控制电压施加到钳位晶体管的栅极。

公开(公告)号：US07453739B2

公开(公告)日：2008-11-18

申请号：US11742600

申请日：2007-05-01

申请人： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

发明人： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC分类号： G11C7/10

CPC分类号： G11C16/3459 ,  G06F3/0659 ,  G06F12/0246 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/104 ,  G11C2216/14

摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

摘要翻译： 在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否 或者不是第二操作是可执行的。

公开(公告)号：US20080200490A1

公开(公告)日：2008-08-21

申请号：US11917218

申请日：2006-06-09

申请人： Yoshinobu Hashizume ,  Masako Hirota ,  Sachiko Mihara ,  Hiroshi Nakamura ,  Hiroki Koike ,  Yukari Matsumoto

发明人： Yoshinobu Hashizume ,  Masako Hirota ,  Sachiko Mihara ,  Hiroshi Nakamura ,  Hiroki Koike ,  Yukari Matsumoto

IPC分类号： A61K31/438 ,  C07D491/20 ,  A61P35/04

CPC分类号： C07D451/06

摘要： This invention provides the compounds of formula (I), or a pharmaceutically acceptable salt thereof, wherein R1 and R2 independently represent hydrogen or the like; R3 and R4 independently represents hydrogen or the like; R5 represents aryl or the like; —X—Y— represents —CH2O— or the like; and n represents 0, 1 or 2. These compounds have ORL1-receptor antagonist activity; and therefore, are useful to treat diseases or conditions such as pain, various CNS diseases etc.

摘要翻译： 本发明提供式（I）化合物或其药学上可接受的盐，其中R 1和R 2独立代表氢或类似物; R 3和R 4独立地表示氢等; R 5表示芳基等; -X-Y-表示-CH 2 O-等; 并且n表示0,1或2.这些化合物具有ORL1受体拮抗剂活性; 因此，可用于治疗诸如疼痛，各种CNS疾病等疾病或病症。

公开(公告)号：US07380718B2

公开(公告)日：2008-06-03

申请号：US11316546

申请日：2005-12-21

申请人： Hiroshi Nakamura

发明人： Hiroshi Nakamura

IPC分类号： G06K7/10

CPC分类号： G06K7/1456 ,  G06K7/14 ,  G06K7/1486

摘要： To provide a method for reading out symbol information and a device for reading out symbol information which are able to prevent a decline in decoding reliability by reducing noise caused by a quantized error, localized contaminations or the like. The method for reading out symbol information may comprise a process in which the image data, obtained by imaging the symbol information such as bar codes and the like, are converted to corrected image data having zero angle of inclination; a smoothing process in which the corrected image data are smoothed; and a column specifying process in which breakpoints of said symbol information column are specified by computing the total sum in the row direction on the smoothed corrected image data.

摘要翻译： 提供一种读出符号信息的方法和用于读出能够通过减少由量化误差，局部污染等引起的噪声而能够防止解码可靠性下降的符号信息的装置。 用于读出符号信息的方法可以包括将通过对诸如条形码等的符号信息进行成像而获得的图像数据转换为具有零倾角的校正图像数据的处理; 平滑处理，其中校正的图像数据被平滑化; 以及列指定处理，其中通过计算平滑校正图像数据上的行方向上的总和来指定所述符号信息列的断点。

公开(公告)号：US07379340B2

公开(公告)日：2008-05-27

申请号：US11318524

申请日：2005-12-28

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

摘要翻译： 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。

公开(公告)号：US07371102B2

公开(公告)日：2008-05-13

申请号：US11178591

申请日：2005-07-12

申请人： Nobuyuki Sakamoto ,  Shigeru Tanaka ,  Hiroshi Nakamura ,  Makoto Yamanashi ,  Atsushi Nishida ,  Masato Minakata ,  Hiroshi Kobayashi

发明人： Nobuyuki Sakamoto ,  Shigeru Tanaka ,  Hiroshi Nakamura ,  Makoto Yamanashi ,  Atsushi Nishida ,  Masato Minakata ,  Hiroshi Kobayashi

IPC分类号： H01R13/627

CPC分类号： H01R13/6275 ,  H01R13/639

摘要： In a connector lock structure 1 provided at female and male connectors which can be fitted together, the female connector 2 has an engagement portion 14, and a slide lock member 13 is supported on the male connector 3 so as to move at least in connector-inserting and connector-withdrawing directions. The slide lock member 13 includes a retaining portion 16 for engagement with the engagement portion 14, and urging member 36 for urging the slide lock member 13. When the engagement portion 14 reaches an engagement position where it is engaged with the retaining portion 16 at the time when the female and male connectors are completely fitted together, the slide lock member 13 is automatically moved by the urging member 36, so that the retaining portion 16 is engaged with the engagement portion 14.

摘要翻译： 在设置在可以装配在一起的阴连接器和公连接器的连接器锁定结构1中，阴连接器2具有接合部14，并且滑动锁定构件13被支撑在阳连接器3上，以便至少在连接器 - 插入和连接器撤回方向。 滑动锁定构件13包括用于与接合部分14接合的保持部分16和用于推动滑动锁定构件13的推动构件36。 当接合部分14在阴和阳连接器完全装配在一起时达到与保持部分16接合的接合位置时，滑动锁定构件13被推动构件36自动移动，使得保持 部分16与接合部分14接合。

公开(公告)号：US07335937B2

公开(公告)日：2008-02-26

申请号：US10914422

申请日：2004-08-10

申请人： Hiroshi Nakamura ,  Kenichi Imamiya

发明人： Hiroshi Nakamura ,  Kenichi Imamiya

IPC分类号： H01L29/76

CPC分类号： H01L27/11526 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/115 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.

摘要翻译： 在由多个存储单元串联连接的NAND单元组成的EEPROM中，通过数据读取操作选择的块中的存储单元的控制栅极电压V SUB读取不同于 所选块中选择晶体管的选择栅极的电压V SUB，V S s2，...，以使得可以实现高速读取而不带来 关于介于选择栅极和选择晶体管的沟道之间的绝缘膜的击穿。 如果使存储器单元的控制栅极电压与选择的电压不同，则也可以在DINOR单元，AND单元，NOR单元和与其连接的单个存储单元的NAND单元中实现高速读数。 选择晶体管的栅极。