公开(公告)号：US20070076477A1

公开(公告)日：2007-04-05

申请号：US11243771

申请日：2005-10-05

申请人： Jiunn-Ren Hwang ,  Min-Hwa Chi ,  Fu-Liang Yang

发明人： Jiunn-Ren Hwang ,  Min-Hwa Chi ,  Fu-Liang Yang

IPC分类号： G11C14/00

CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42348 ,  H01L29/785 ,  H01L29/7923

摘要： A 2-bit FinFET flash memory cell capable of storing 2 bits and a method of forming the same are provided. The memory cell includes a semiconductor fin on a top surface of a substrate, a gate insulation film on the top surface and sidewalls of a channel section of the semiconductor fin, a gate electrode on the gate insulation film, and two charge-trapping regions along opposite sides of the gate electrode, wherein each charge-trapping region is separated from the gate electrode and the semiconductor fin by a tunneling layer. The memory cell further includes a protective layer on the charge-trapping regions. Each of the two charge-trapping regions is capable of storing one bit. The memory cell can be operated by applying different bias voltages to the source, the drain, and the gate of the memory cell.

摘要翻译： 提供能够存储2位的2位FinFET闪存单元及其形成方法。 存储单元包括在衬底的顶表面上的半导体鳍片，顶表面上的栅极绝缘膜和半导体鳍片的沟道部分的侧壁，栅极绝缘膜上的栅电极和沿着两个电荷捕获区域 栅电极的相对侧，其中每个电荷俘获区域通过隧道层与栅极电极和半导体鳍片分离。 存储单元还包括在电荷捕获区上的保护层。 两个电荷捕获区域中的每一个能够存储一个位。 可以通过向存储器单元的源极，漏极和栅极施加不同的偏置电压来操作存储器单元。

公开(公告)号：US20060281254A1

公开(公告)日：2006-12-14

申请号：US11148342

申请日：2005-06-09

申请人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

发明人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/2815 ,  H01L21/28273 ,  H01L29/42324

摘要： A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.

摘要翻译： 一种用于在用于高速RAM应用的浮动栅极的两侧上制造侧壁控制栅极的自对准导电间隔物工艺，其可以很好地限定侧壁控制栅极的尺寸和轮廓。 在电介质层上形成导电层，以覆盖图案化在半导体衬底上的浮动栅极。 在与浮动栅极的侧壁相邻的导电层上形成氧化物间隔物。 在导电层上进行各向异性蚀刻处理并使用氧化物间隔物作为硬掩模，导电间隔物在浮栅的两侧制造，用作侧壁控制栅极。

公开(公告)号：US20060183031A1

公开(公告)日：2006-08-17

申请号：US11380192

申请日：2006-04-25

申请人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

发明人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

IPC分类号： G03C5/00 ,  G03F1/00

CPC分类号： G03F1/36 ,  G03F1/26

摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.

摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。

公开(公告)号：US07063923B2

公开(公告)日：2006-06-20

申请号：US10711198

申请日：2004-09-01

申请人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

发明人： Jiunn-Ren Hwang ,  Jui-Tsen Huang ,  Chang-Jyh Hsieh

IPC分类号： G03F9/00

CPC分类号： G03F1/36 ,  G03F1/26

摘要： An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.

摘要翻译： 集成电路布局包括密集图形和至少一个独立的图形。 形成多个虚拟图形以围绕隔离图，以便减小集成电路布局的图案密度的差异。 伪图案的透射光相对于集成电路布局的透射光提供0或180度的相位差。 集成电路布局和多个虚拟图案形成在光掩模上。

公开(公告)号：US06589881B2

公开(公告)日：2003-07-08

申请号：US09997339

申请日：2001-11-27

申请人： I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Kuei-Chun Hung ,  Ching-Hsu Chang

发明人： I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Kuei-Chun Hung ,  Ching-Hsu Chang

IPC分类号： H01L21302

CPC分类号： H01L21/76835 ,  H01L21/76807 ,  H01L21/76813

摘要： A method of forming a dual damascene structure. A substrate having a conductive layer thereon is provided. A passivation layer, a first dielectric layer, an etching stop layer, a second dielectric layer and cap layer serving as a base anti-reflection coating are sequentially formed over the substrate. The cap layer and the second dielectric layer are patterned to form a first opening that exposes a portion of the etching stop layer. A patterned negative photoresist layer having a second opening therein is formed above the cap layer. The cap layer exposed by the second opening and the second dielectric layer exposed by the first opening are removed. Thereafter, the second dielectric layer exposed by the second opening is removed to form a trench and the first dielectric layer exposed by the first opening is removed to form a via opening. The passivation layer exposed by via opening and then the negative photoresist layer is removed. A conformal barrier layer and a conductive layer are sequentially formed over the trench and the via opening with the conductive layer, completely filling the trench and the via opening.

摘要翻译： 形成双镶嵌结构的方法。 提供其上具有导电层的基板。 在衬底上顺序形成钝化层，第一介电层，蚀刻停止层，第二电介质层和用作基底防反射涂层的覆盖层。 将盖层和第二介电层图案化以形成暴露蚀刻停止层的一部分的第一开口。 在其上方形成了具有第二开口的图案化的负性光致抗蚀剂层。 除去由第二开口暴露的盖层和由第一开口露出的第二介质层。 此后，除去由第二开口露出的第二电介质层以形成沟槽，并且去除由第一开口暴露的第一电介质层以形成通孔。 去除通过开口暴露的钝化层，然后去除负的光致抗蚀剂层。 在沟槽和通孔开口上依次形成保形阻挡层和导电层，导电层完全填充沟槽和通孔。

公开(公告)号：US06579790B1

公开(公告)日：2003-06-17

申请号：US09707314

申请日：2000-11-06

申请人： I-Hsiung Huang ,  Jiunn-Ren Hwang

发明人： I-Hsiung Huang ,  Jiunn-Ren Hwang

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/0274

摘要： A method of fabricating a dual damascene opening in a dielectric layer above a substrate. A first photoresist layer having a first opening therein is formed over the dielectric layer. The first opening exposes the dielectric layer at a position where a via is desired. A buffer layer is formed over the first photoresist layer. A second photoresist layer having a second opening is formed over the buffer layer. The second opening exposes the area where a conductive wire is desired. The first opening and the second opening together form a metallic interconnect structure. Using the first and the second photoresist layer as a mask, a dual damascene structural opening that includes a via opening and a conductive wire trench is formed in the dielectric layer.

摘要翻译： 在衬底上方的电介质层中制造双镶嵌开口的方法。 在电介质层上方形成有第一开口的第一光致抗蚀剂层。 第一开口将电介质层暴露在期望通孔的位置处。 在第一光致抗蚀剂层上形成缓冲层。 在缓冲层上形成具有第二开口的第二光致抗蚀剂层。 第二个开口露出需要导线的区域。 第一开口和第二开口一起形成金属互连结构。 使用第一和第二光致抗蚀剂层作为掩模，在电介质层中形成包括通孔开口和导线沟槽的双镶嵌结构开口。

公开(公告)号：US06541782B2

公开(公告)日：2003-04-01

申请号：US09734240

申请日：2000-12-05

申请人： I-Hsiung Huang ,  Jiunn-Ren Hwang

发明人： I-Hsiung Huang ,  Jiunn-Ren Hwang

IPC分类号： H01L2100

CPC分类号： G03F7/2037 ,  H01J2237/0044 ,  H01J2237/3175 ,  H01J2237/31796

摘要： An electron beam photolithographic process for patterning an insulation layer over a substrate. A conductive photoresist layer having a conjugate structure is formed over the insulation layer. An electron beam photolithographic process is conducted using a photomask so that the pattern on the photomask is transferred to the conductive photoresist layer.

公开(公告)号：US06312855B1

公开(公告)日：2001-11-06

申请号：US09444466

申请日：1999-11-22

申请人： Jiunn-Ren Hwang ,  I-Hsiung Huang ,  Anseime Chen

发明人： Jiunn-Ren Hwang ,  I-Hsiung Huang ,  Anseime Chen

IPC分类号： G03F900

CPC分类号： G03F1/28

摘要： A three-phase phase shift mask. On a transparent substrate, a non-transparent pattern covering a portion of the transparent substrate is formed, while the other portion of the substrate is remained exposed. A proximity region around a comer of the non-transparent pattern is equally partitioned three phase-shift areas different from each other with a phase shift of 120°. The formation of these three phase-shift areas uses two etching steps to form a first and a second phase-shift areas, while a portion of the exposed substrate is etched twice as a third phase-shift area.

摘要翻译： 三相相移掩模。 在透明基板上，形成覆盖透明基板的一部分的不透明图案，同时基板的另一部分保持露出。 不透明图案的周围的邻近区域被相等地划分为相位相差120°的三个相移区域。 这三个相移区域的形成使用两个蚀刻步骤来形成第一和第二相移区域，而暴露的衬底的一部分被蚀刻两次作为第三相移区域。