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292 条记录 (耗时 0.035 秒)

    Semiconductor Contact Barrier
    52.
    发明申请
    Semiconductor Contact Barrier 有权
    半导体接触屏障

    公开(公告)号：US20110121410A1

    公开(公告)日：2011-05-26

    申请号：US13015328

    申请日：2011-01-27

    申请人： Chung-Shi Liu ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Chen-Hua Yu

    IPC分类号： H01L29/78 ,  H01L23/532

    CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76856 ,  H01L23/485 ,  H01L29/665 ,  H01L29/7833

    摘要： System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.

    摘要翻译： 提供了降低接触电阻和改善阻隔性能的系统和方法。 一个实施例包括介电层和延伸穿过电介质层的连接到导电区域的触点。 在通过用于接触的电介质层形成开口之后，在导电区域和触点之间通过无电解电镀导电区域形成接触阻挡层。 然后处理接触阻挡层以填充接触阻挡层的晶界，从而提高接触电阻。 在另一个实施例中，接触阻挡层通过在形成电介质层之前的无电镀形成在导电区上。

    Methods for forming interconnect structures that include forming air gaps between conductive structures
    53.
    发明授权
    Methods for forming interconnect structures that include forming air gaps between conductive structures 有权
    形成互连结构的方法，其包括在导电结构之间形成气隙

    公开(公告)号：US07871922B2

    公开(公告)日：2011-01-18

    申请号：US11733556

    申请日：2007-04-10

    申请人： Chung-Shi Liu ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Chen-Hua Yu

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76849 ,  H01L21/76867

    摘要： A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric layer, at least partially removing the sacrificial layer and forming at least one air gap between two of the conductive structures. A surface of the first dielectric layer is treated, forming a second dielectric layer over the first dielectric layer, after the formation of the air gap. A third dielectric layer is formed over the second dielectric layer. At least one opening is formed within the third dielectric layer such that the second dielectric layer substantially protects the first dielectric layer from damage by the step of forming the opening.

    摘要翻译： 一种用于形成半导体结构的方法包括在衬底上形成牺牲层。 在牺牲层上形成第一介电层。 在牺牲层和第一介电层内形成多个导电结构。 牺牲层通过第一介电层进行处理，至少部分去除牺牲层并在两个导电结构之间形成至少一个气隙。 处理第一电介质层的表面，在形成气隙之后在第一介电层上形成第二电介质层。 在第二电介质层上形成第三电介质层。 至少一个开口形成在第三电介质层内，使得第二电介质层基本上保护第一电介质层不受形成开口的步骤的损害。

    Integrated circuit and manufacturing method of copper germanide and copper silicide as copper capping layer
    55.
    发明授权
    Integrated circuit and manufacturing method of copper germanide and copper silicide as copper capping layer 有权
    锗锗和铜硅化铜作为铜覆盖层的集成电路和制造方法

    公开(公告)号：US07858519B2

    公开(公告)日：2010-12-28

    申请号：US12264095

    申请日：2008-11-03

    申请人： Chung-Shi Liu ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Chen-Hua Yu

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76849 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided for forming a capping layer comprising Cu, N, and also Si and/or Ge onto a copper conductive structure, said method comprising the sequential steps of: forming, at a temperature range between 200° C. up to 400° C., at least one capping layer onto said copper conductive structure by exposing said structure to a GeH4 and/or a SiH4 comprising ambient, performing a NH3 plasma treatment thereby forming an at least partly nitrided capping layer, forming a dielectric barrier layer onto said at least partly nitrided capping layer, wherein prior to said step of forming said at least one capping layer a pre-annealing step of said copper conductive structure is performed at a temperature range between 250° C. up to 450° C.

    摘要翻译： 提供了一种用于在铜导电结构上形成包含Cu，N以及Si和/或Ge的覆盖层的方法，所述方法包括以下顺序步骤：在200℃至400℃的温度范围内 通过将所述结构暴露于包含环境的GeH 4和/或SiH 4，执行NH 3等离子体处理从而形成至少部分氮化的覆盖层，在所述铜导电结构上至少一个覆盖层，在所述铜导电结构上形成介电阻挡层 至少部分氮化的覆盖层，其中在形成所述至少一个覆盖层的所述步骤之前，所述铜导电结构的预退火步骤在250℃至450℃的温度范围内进行。

    Advanced metal gate method and device
    56.
    发明授权
    Advanced metal gate method and device 有权
    先进的金属门法和器件

    公开(公告)号：US07799628B2

    公开(公告)日：2010-09-21

    申请号：US12354558

    申请日：2009-01-15

    申请人： Chung-Shi Liu ,  Hsiang-Yi Wang ,  Cheng-Tung Lin ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Hsiang-Yi Wang ,  Cheng-Tung Lin ,  Chen-Hua Yu

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28088 ,  H01L21/265 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/78

    摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.

    摘要翻译： 本公开提供一种制造半导体器件的方法，其包括在衬底上形成高k电介质，在高k电介质上形成第一金属层，在第一金属层上形成第二金属层，形成第一硅 在所述第二金属层上方，将多个离子注入到所述第一硅层中，并且所述第二金属层覆盖在所述基板的第一区域上，在所述第一硅层上形成第二硅层，在所述第一区上形成第一栅极结构 以及在第二区域上的第二栅极结构，执行使所述第二金属层与所述第一硅层反应以在所述第一和第二栅极结构中分别形成硅化物层的退火处理，并将所述离子驱动到 第一栅极结构中的第一金属层和高k电介质。

    Method of Forming Via Recess in Underlying Conductive Line
    58.
    发明申请
    Method of Forming Via Recess in Underlying Conductive Line 审中-公开
    在导电线路中通过凹陷形成的方法

    公开(公告)号：US20100159693A1

    公开(公告)日：2010-06-24

    申请号：US12715175

    申请日：2010-03-01

    申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Horng-Huei Tseng

    发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Horng-Huei Tseng

    IPC分类号： H01L21/768

    CPC分类号： H01L23/5329 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the conductive line at the via. The via recess in the conductive line has a depth ranging from about 100 angstroms to about 600 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.

    摘要翻译： 制造半导体器件的方法包括在介电层下方形成导电线的电介质层中形成通孔，以及在通孔的导电线中形成通路凹槽。 导线中的通路凹槽的深度范围为约100埃至约600埃。 通孔填充材料填充通孔凹部并且至少部分地填充通孔，使得通孔填充材料电连接到导电线。 例如，通孔凹部可以具有与通孔相同的尺寸或更小的横截面面积。 例如，这种通孔结构可以是金属间电介质结构中的双镶嵌结构的一部分。

    Method of forming via recess in underlying conductive line
    60.
    发明申请
    Method of forming via recess in underlying conductive line 审中-公开
    在下面的导线中形成通孔凹槽的方法

    公开(公告)号：US20070117374A1

    公开(公告)日：2007-05-24

    申请号：US11652210

    申请日：2007-01-11

    申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Horng-Huei Tseng

    发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Horng-Huei Tseng

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5329 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the conductive line at the via. The via recess in the conductive line has a depth ranging from about 100 angstroms to about 600 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.

    摘要翻译： 制造半导体器件的方法包括在介电层下方形成导电线的电介质层中形成通孔，以及在通孔中的导电线中形成通路凹槽。 导线中的通路凹槽的深度范围为约100埃至约600埃。 通孔填充材料填充通孔凹部并且至少部分地填充通孔，使得通孔填充材料电连接到导电线。 例如，通孔凹部可以具有与通孔相同的尺寸或更小的横截面面积。 例如，这种通孔结构可以是金属间电介质结构中的双镶嵌结构的一部分。