公开(公告)号：US20120070029A1

公开(公告)日：2012-03-22

申请号：US12884137

申请日：2010-09-16

申请人： Daniel Gregory Muriello ,  Stephen Charles Heise ,  Jie Chen

发明人： Daniel Gregory Muriello ,  Stephen Charles Heise ,  Jie Chen

IPC分类号： G06K9/00

CPC分类号： G06F21/44

摘要： Users of an online system are authenticated based on signatures of cameras that were used to capture images uploaded to the online system. Users of an online system upload photos taken from their cameras. The online system extracts characteristic information about the camera that captured the photos. This information includes a mapping of faulty pixels, metadata included with the photos, a naming convention, and the like. The online system stores an association between the user and the camera. This association is used for authentication of the user. For authentication, the user is asked to upload new photos taken from the camera that the user used previously. The information extracted from the newly uploaded photos is matched against stored information of cameras used previously by the user. The user is successfully authenticated if the camera used for the newly uploaded photos matches a previously stored camera.

摘要翻译： 在线系统的用户基于用于捕获上传到在线系统的图像的相机的签名进行身份验证。 在线系统的用户上传从相机拍摄的照片。 在线系统提取拍摄照片的相机的特征信息。 该信息包括错误像素的映射，照片附带的元数据，命名约定等。 在线系统存储用户和相机之间的关联。 该关联用于用户的认证。 对于认证，用户被要求上传用户以前使用的相机拍摄的新照片。 从新上传的照片提取的信息与用户先前使用的相机的存储信息相匹配。 如果用于新上传的照片的相机与先前存储的相机匹配，则用户已成功验证。

公开(公告)号：US08138785B2

公开(公告)日：2012-03-20

申请号：US12586288

申请日：2009-09-18

申请人： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

发明人： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521

摘要： A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

摘要翻译： 公开了一种用于PC架构的时钟驱动电路和驱动多条输出线的方法。 时钟驱动电路包括一个时钟发生电路，该时钟发生电路耦合到用于PC的输出缓冲器，该输出缓冲器具有连接到具有输出负载阻抗的多个输出负载的多条输出线。 输出线在低于电源电压的输出电压下差分驱动。 该电路包括具有电压节点阻抗的电压节点。 电压节点维持在基本上的输出电压。 该电路包括吸收来自电压节点的电流的电流吸收晶体管。 电流吸收晶体管以由电流吸收晶体管的尺寸确定的欧姆电阻为特征的线性区域工作。 通过调整电流吸收晶体管的尺寸，将电压节点的阻抗与负载阻抗之一相匹配。

公开(公告)号：US08133070B2

公开(公告)日：2012-03-13

申请号：US12636172

申请日：2009-12-11

申请人： Chih Yu Hsueh ,  Jie Chen

发明人： Chih Yu Hsueh ,  Jie Chen

IPC分类号： H01R12/24

CPC分类号： H01R9/03 ,  H01R12/57 ,  H01R12/7052 ,  H01R12/707 ,  H01R12/716 ,  H01R13/506

摘要： A SATA electrical connector extends a lateral rib and a longitudinal guiding portion from a base surface of an insulator. The insulator and the terminals have intimate engagements, for minimizing height and width of the entire structure. The electrical connector can be joined to another electrical connector for forming an electrical connector assembly.

公开(公告)号：US20120059287A1

公开(公告)日：2012-03-08

申请号：US13293907

申请日：2011-11-10

申请人： Tarek Hessin Ahmed El-Bialy ,  Jie Chen ,  Ying Yin Tsui

发明人： Tarek Hessin Ahmed El-Bialy ,  Jie Chen ,  Ying Yin Tsui

IPC分类号： A61N7/00

CPC分类号： A61N7/00 ,  A61B2017/00106 ,  A61B2017/00734 ,  A61B2090/378 ,  A61C8/0006 ,  A61C19/06 ,  C12M35/04 ,  C12N13/00

摘要： Ultrasound stimulation devices and related techniques are disclosed. An ultrasound transducer for generating ultrasound energy is carried by a transducer housing that seals the transducer and may also include a positioning element for positioning the transducer proximate an application area to which generated ultrasound energy is to be applied. The transducer housing may also carry such components as a battery, a wireless receiver, and a controller. The same housing or a separate sensor housing may include an ultrasound sensor that provides feedback to the ultrasound transducer or its controller, illustratively through a wireless transmitter.

公开(公告)号：US20110261865A1

公开(公告)日：2011-10-27

申请号：US12806556

申请日：2010-08-16

申请人： Jie Chen ,  Keshab K. Parhi

发明人： Jie Chen ,  Keshab K. Parhi

IPC分类号： H04B15/00 ,  H04L27/01 ,  H04B1/38

CPC分类号： H04L25/03343 ,  H04L25/03057

摘要： The present invention relates to data processing techniques in multi-channel data transmission systems. In this invention, a novel approach is proposed to deal with FEXT interferences in the application of high/ultra-high speed Ethernet systems. Compared with the traditional FEXT cancellation approaches, the proposed FEXT canceller can deal with the non-causal part of FEXT, and thus can achieve better cancellation performance. Instead of using the conventional DFE, structure, TH precoding technique is incorporated into the proposed design to alleviate the error propagation problem. The resulting FEXT cancellers do not contain feedback loops which makes the high speed VLSI implementation easy. A modified design is also developed by using a finite signal as the input to the FEXT canceller such that the hardware complexity of the proposed FEXT canceller can be reduced.

摘要翻译： 本发明涉及多通道数据传输系统中的数据处理技术。 在本发明中，提出了一种新颖的方法来处理高/超高速以太网系统的应用中的FEXT干扰。 与传统的FEXT取消方法相比，提出的FEXT消除器可以处理FEXT的非因果部分，从而可以实现更好的取消性能。 代替使用常规的DFE，结构，TH预编码技术被并入所提出的设计中以减轻误差传播问题。 所产生的FEXT消除器不包含使得高速VLSI实现变得容易的反馈回路。 还通过使用有限信号作为FEXT消除器的输入来开发修改的设计，使得可以减少所提出的FEXT消除器的硬件复杂性。

公开(公告)号：US20110223811A1

公开(公告)日：2011-09-15

申请号：US13114661

申请日：2011-05-24

申请人： Chih Yu Hsueh ,  Jie Chen

发明人： Chih Yu Hsueh ,  Jie Chen

IPC分类号： H01R24/00 ,  H01R13/04

CPC分类号： H01R9/03 ,  H01R12/57 ,  H01R12/7052 ,  H01R12/707 ,  H01R12/716 ,  H01R13/506

摘要： A SATA electrical connector extends a lateral rib and a longitudinal guiding portion from a base surface of an insulator. The insulator and the terminals have intimate engagements, for minimizing height and width of the entire structure. The electrical connector can be joined to another electrical connector for forming an electrical connector assembly.

摘要翻译： SATA电连接器从绝缘体的基面延伸横向肋和纵向引导部分。 绝缘体和端子具有紧密接合，用于最小化整个结构的高度和宽度。 电连接器可以连接到用于形成电连接器组件的另一个电连接器。

公开(公告)号：US20110098502A1

公开(公告)日：2011-04-28

申请号：US12811418

申请日：2008-01-01

申请人： Jiankang Xu ,  Da Zhang ,  Meiqi Ye ,  Jie Chen ,  Yongbing Guo ,  Yongjiang Hu

发明人： Jiankang Xu ,  Da Zhang ,  Meiqi Ye ,  Jie Chen ,  Yongbing Guo ,  Yongjiang Hu

IPC分类号： C07C227/36

CPC分类号： C07C227/34 ,  C07C229/08

摘要： The present invention relates to a process for resolving S-3-(Aminomethyl)-5-methylhexanoic acid, which adopts benzoyl-L-glutamic acid, 4-methyl benzoyl-L-glutamic acid, benzene sulfonyl-L-glutamic acid or 4-methyl benzene sulfonyl-L-glutamic acid as a resolution agent to make a first resolution to racemic 3-aminomethyl-5-methylhexanoic acid, and adopts the resolution agent same to that of the first resolution to make a second resolution to the first resolution product to obtain the second resolution product, thus the resolution salt product is obtained, and further hydrolyzed by an acid, the resolution agent is extracted to be separated, the pH is adjusted to be neutral, the product S-3-(Aminomethyl)-5-methylhexanoic acid, i.e. the pregabalin, is then precipitated by distillation, therefore the present invention has the characteristics of polluting the environment slightly, high efficiency and stability, simpleness and practicality, producing product with high purity and a low sproduction cost, and is suitable for large-scale production.

摘要翻译： 本发明涉及一种分离S-3-（氨基甲基）-5-甲基己酸的方法，该方法采用苯甲酰基-L-谷氨酸，4-甲基苯甲酰基-L-谷氨酸，苯磺酰基-L-谷氨酸或4 甲基苯磺酰基-L-谷氨酸作为拆分剂，首先拆分为外消旋的3-氨基甲基-5-甲基己酸，并采用与第一分辨率相同的分解剂，以第一分辨率作第二分辨率 得到第二分解产物，得到分解盐产物，并进一步用酸水解，提取分离剂分离，将pH调节为中性，产物S-3-（氨基甲基） - 然后通过蒸馏沉淀5-甲基己酸，即普瑞巴林，因此本发明具有轻微，高效和稳定，简单和实用的污染环境的特点，生产高纯度和低产量的产品 成本高，适合大规模生产。

公开(公告)号：US20110044448A1

公开(公告)日：2011-02-24

申请号：US12806539

申请日：2010-08-16

申请人： Jie Chen ,  Keshab K. Parhi

发明人： Jie Chen ,  Keshab K. Parhi

IPC分类号： H04M9/08

CPC分类号： H04B3/23

摘要： The present invention relates to design and implementation of low complexity adaptive echo and NEXT cancellers in multi-channel data transmission systems. In this invention, a highly efficient weight update scheme is proposed to reduce the computational cost of the weight update part in adaptive echo and NEXT cancellers. Based on the proposed scheme, the hardware complexity of the weight update part can be further reduced by applying the word-length reduction technique. The proposed scheme is general and suitable for real applications such as design of a low complexity transceiver in 10GBase-T. Different with prior work, this invention considers the complexity reduction in weight update part of the adaptive filters such that the overall complexity of these adaptive cancellers can be significantly reduced.

摘要翻译： 本发明涉及多通道数据传输系统中低复杂度自适应回波和NEXT消除器的设计和实现。 在本发明中，提出了一种高效的加权更新方案，以减少自适应回波和NEXT消除器中权重更新部分的计算成本。 基于所提出的方案，可以通过应用字长缩减技术来进一步降低权重更新部分的硬件复杂度。 所提出的方案是一般的，适用于实际应用，例如在10GBase-T中设计低复杂度收发器。 与现有技术不同，本发明考虑了自适应滤波器的权重更新部分的复杂度降低，使得这些自适应消除器的整体复杂度可以显着降低。

公开(公告)号：US20100148817A1

公开(公告)日：2010-06-17

申请号：US12586288

申请日：2009-09-18

申请人： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

发明人： Jie Chen ,  Ting-Yen Chiang ,  Kuang-Yu Chen ,  Chen Yu Wang ,  Joe Froniewski

IPC分类号： H03K19/003 ,  H03K19/094

CPC分类号： H03K19/018521

摘要： A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

摘要翻译： 公开了一种用于PC架构的时钟驱动电路和驱动多条输出线的方法。 时钟驱动电路包括一个时钟发生电路，该时钟发生电路耦合到用于PC的输出缓冲器，该输出缓冲器具有连接到具有输出负载阻抗的多个输出负载的多条输出线。 输出线在低于电源电压的输出电压下差分驱动。 该电路包括具有电压节点阻抗的电压节点。 电压节点维持在基本上的输出电压。 该电路包括吸收来自电压节点的电流的电流吸收晶体管。 电流吸收晶体管以由电流吸收晶体管的尺寸确定的欧姆电阻为特征的线性区域工作。 通过调整电流吸收晶体管的尺寸，将电压节点的阻抗与负载阻抗之一相匹配。

公开(公告)号：US20100035234A1

公开(公告)日：2010-02-11

申请号：US12468779

申请日：2009-05-19

申请人： John Donnelly ,  Ping Wu ,  George Santos ,  Marzia Monica Giuliani ,  William Andrews ,  Jie Chen

发明人： John Donnelly ,  Ping Wu ,  George Santos ,  Marzia Monica Giuliani ,  William Andrews ,  Jie Chen

IPC分类号： C12Q1/70 ,  G01N33/569 ,  G01N33/574 ,  G01N33/571

CPC分类号： G01N33/569 ,  G01N33/53 ,  G01N2333/205 ,  G01N2333/22 ,  G01N2333/245 ,  G01N2333/285 ,  G01N2333/31 ,  G01N2333/315

摘要： The present invention is directed to methods, assays and compositions for implementing such methods and assays for assessing efficacy of individual components in multi-component vaccines and for assessing efficacy of a vaccine against a pathogen. In one aspect, the method of assessing efficacy of a vaccine against a pathogen is a quick assay that tests for an activity correlated with efficacy such as binding in an ELISA rather than requiring the time and expense of an assay that detects actual bactericidal activity. In another aspect, the method for testing the efficacy of an individual component in a multi-component vaccine includes obtaining an immune sample from a subject inoculated with the multi-component vaccine; blocking the portion of the immune sample that recognizes the individual component such as by addition of the individual component, and testing the efficacy of the immune sample to respond to the pathogen.

摘要翻译： 本发明涉及用于实施用于评估多组分疫苗中各个组分的功效并用于评估针对病原体的疫苗的功效的这些方法和测定的方法，测定和组合物。 在一个方面，评估疫苗针对病原体的功效的方法是测试与功效相关的活性的快速测定，例如在ELISA中的结合，而不是需要检测实际杀菌活性的测定的时间和费用。 另一方面，用于测试多组分疫苗中单个组分的功效的方法包括从接种多组分疫苗的受试者获得免疫样品; 阻止识别个体成分的免疫样品的部分，例如通过加入各个组分，以及测试免疫样品对病原体的反应的功效。