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119 条记录 (耗时 0.041 秒)

    Methods of Manufacturing Stacked Semiconductor Devices
    53.
    发明申请
    Methods of Manufacturing Stacked Semiconductor Devices 审中-公开
    堆叠半导体器件制造方法

    公开(公告)号：US20110237055A1

    公开(公告)日：2011-09-29

    申请号：US13053291

    申请日：2011-03-22

    申请人： Yong-hoon Son ,  Si-Young Choi ,  Myoung-Bum Lee ,  Ki-Hyun Hwang ,  Seung-Jae Baik ,  Jeong Hee Han

    发明人： Yong-hoon Son ,  Si-Young Choi ,  Myoung-Bum Lee ,  Ki-Hyun Hwang ,  Seung-Jae Baik ,  Jeong Hee Han

    IPC分类号： H01L21/20

    CPC分类号： H01L27/11578 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1207

    摘要： A stacked semiconductor device that is reliable by forming an insulating layer on a lower memory layer and by forming a single crystalline semiconductor in portions of the insulating layer. A method of manufacturing the stacked semiconductor device, including: providing a lower memory layer including a plurality of lower memory structures; forming an insulating layer on the lower memory layer; forming trenches by removing portions of the insulating layer; forming a preparatory semiconductor layer for filling the trenches; and forming a single crystalline semiconductor layer by phase-changing the preparatory semiconductor layer.

    摘要翻译： 通过在下部存储层上形成绝缘层，在绝缘层的一部分形成单晶半导体，可靠的叠层型半导体装置。 一种制造叠层半导体器件的方法，包括：提供包括多个下部存储结构的下部存储层; 在下部存储层上形成绝缘层; 通过去除绝缘层的部分形成沟槽; 形成用于填充沟槽的准备半导体层; 以及通过相变所述预备半导体层来形成单晶半导体层。

    Method and device for forming an STI type isolation in a semiconductor device
    54.
    发明授权
    Method and device for forming an STI type isolation in a semiconductor device 失效
    在半导体器件中形成STI型隔离的方法和装置

    公开(公告)号：US06835996B2

    公开(公告)日：2004-12-28

    申请号：US10684451

    申请日：2003-10-15

    申请人： Chul-Sung Kim ,  Si-Young Choi ,  Jung-Woo Park ,  Jong-Ryol Ryu ,  Byeong-Chan Lee

    发明人： Chul-Sung Kim ,  Si-Young Choi ,  Jung-Woo Park ,  Jong-Ryol Ryu ,  Byeong-Chan Lee

    IPC分类号： H01L2900

    CPC分类号： H01L21/76224

    摘要： A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

    摘要翻译： 半导体器件中的沟槽隔离及其制造方法包括：在硅衬底中形成具有用于器件隔离的内侧壁的沟槽; 在形成沟槽的内侧壁的硅衬底的表面上形成氧化物层; 向硅衬底提供愈合元件以去除悬挂键; 并用器件隔离层填充沟槽，从而形成沟槽隔离，而不产生悬挂键导致电荷陷阱。

    Method and device for forming an STI type isolation in a semiconductor device
    55.
    发明授权
    Method and device for forming an STI type isolation in a semiconductor device 失效
    在半导体器件中形成STI型隔离的方法和装置

    公开(公告)号：US06849520B2

    公开(公告)日：2005-02-01

    申请号：US10685518

    申请日：2003-10-16

    申请人： Chul-Sung Kim ,  Si-Young Choi ,  Jung-Woo Park ,  Jong-Ryol Ryu ,  Byeong-Chan Lee

    发明人： Chul-Sung Kim ,  Si-Young Choi ,  Jung-Woo Park ,  Jong-Ryol Ryu ,  Byeong-Chan Lee

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76224

    摘要： A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

    摘要翻译： 半导体器件中的沟槽隔离及其制造方法包括：在硅衬底中形成具有用于器件隔离的内侧壁的沟槽; 在形成沟槽的内侧壁的硅衬底的表面上形成氧化物层; 向硅衬底提供愈合元件以去除悬挂键; 并用器件隔离层填充沟槽，从而形成沟槽隔离，而不产生悬挂键导致电荷陷阱。

    Method and device for forming an STI type isolation in a semiconductor device
    56.
    发明授权
    Method and device for forming an STI type isolation in a semiconductor device 失效
    在半导体器件中形成STI型隔离的方法和装置

    公开(公告)号：US06660613B2

    公开(公告)日：2003-12-09

    申请号：US10102997

    申请日：2002-03-22

    申请人： Chul-Sung Kim ,  Si-Young Choi ,  Jung-Woo Park ,  Jong-Ryol Ryu ,  Byeong-Chan Lee

    发明人： Chul-Sung Kim ,  Si-Young Choi ,  Jung-Woo Park ,  Jong-Ryol Ryu ,  Byeong-Chan Lee

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

    摘要翻译： 半导体器件中的沟槽隔离及其制造方法包括：在硅衬底中形成具有用于器件隔离的内侧壁的沟槽; 在形成沟槽的内侧壁的硅衬底的表面上形成氧化物层; 向硅衬底提供愈合元件以去除悬挂键; 并用器件隔离层填充沟槽，从而形成沟槽隔离，而不产生悬挂键导致电荷陷阱。

    Method of manufacturing a non-volatile memory device
    59.
    发明授权
    Method of manufacturing a non-volatile memory device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US08114735B2

    公开(公告)日：2012-02-14

    申请号：US11902209

    申请日：2007-09-20

    申请人： Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Seung-Jae Baik ,  Sun-Jung Kim ,  Kwang-Min Park ,  In-Sun Yi

    发明人： Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Seung-Jae Baik ,  Sun-Jung Kim ,  Kwang-Min Park ,  In-Sun Yi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/792 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/3185 ,  H01L29/4234 ,  H01L29/518 ,  H01L29/7923

    摘要： In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.

    摘要翻译： 在制造非易失性存储器件的方法中，隧道绝缘层可以形成在衬底的沟道区上。 可以在隧道绝缘层上形成包括氮化硅的电荷俘获层，以从沟道区捕获电子。 可以使用包括氮气的第一气体和包括氧的第二气体来进行热处理，以去除电荷捕获层中的缺陷位点并致密化电荷捕获层。 可以在热处理的电荷俘获层上形成阻挡层，然后可以在阻挡层上形成导电层。 阻挡层，导电层，热处理电荷捕获层和隧道绝缘层可以被图案化以在沟道区上形成栅极结构。 因此，可以提高包括门结构的非易失性存储器件的数据保持性能和/或可靠性。

    MICROWAVE OVEN
    60.
    发明申请
    MICROWAVE OVEN 有权
    微波炉

    公开(公告)号：US20110147378A1

    公开(公告)日：2011-06-23

    申请号：US12935804

    申请日：2009-04-01

    申请人： Sang-Ryul Lee ,  Kyu-Young Kim ,  Jae-Myung Chin ,  Dong-Han Kim ,  Si-Young Choi ,  Sung-Ho Choi

    发明人： Sang-Ryul Lee ,  Kyu-Young Kim ,  Jae-Myung Chin ,  Dong-Han Kim ,  Si-Young Choi ,  Sung-Ho Choi

    IPC分类号： H05B6/64

    CPC分类号： H05B6/708

    摘要： A microwave oven includes a cavity having a cooking chamber; a magnetron oscillating microwave radiation used for cooking food in the cooking chamber; and a plurality of radiation openings through which the microwave radiation is radiated into the cooking chamber, each of the radiation openings having a length in a direction where the microwave radiation is guided by a waveguide, the length being greater or less than λ/4.

    摘要翻译： 微波炉包括具有烹饪室的空腔; 用于在烹饪室中烹饪食物的磁控管振荡微波辐射; 以及多个辐射开口，微波辐射通过该辐射开口辐射到烹饪室中，每个辐射开口具有在微波辐射被波导引导的方向上的长度，该长度大于或小于λ/ 4。