公开(公告)号：US09190407B2

公开(公告)日：2015-11-17

申请号：US14569597

申请日：2014-12-12

申请人： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

发明人： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/49

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

摘要翻译： 半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。 第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。 第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。 第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。 可以在第二绝缘体的顶表面上形成伪栅电极。 还公开了其制造方法和修改方案。

公开(公告)号：US20120055908A1

公开(公告)日：2012-03-08

申请号：US13220084

申请日：2011-08-29

申请人： Sang-Wuk Park ,  Geum-Jung Seong ,  Kye-Hyun Baek ,  Yong-Jin Kim ,  Chan-Mi Lee

发明人： Sang-Wuk Park ,  Geum-Jung Seong ,  Kye-Hyun Baek ,  Yong-Jin Kim ,  Chan-Mi Lee

IPC分类号： B23K26/36 ,  B23K26/04

CPC分类号： B23K26/0661 ,  B23K26/032 ,  B23K26/361 ,  H01J37/32972 ,  H01L22/12 ,  H01L22/26

摘要： Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.

摘要翻译： 提供了蚀刻系统和控制蚀刻工艺条件的方法。 蚀刻系统包括将入射光照射到目标晶片中的光源，光强度测量单元，其根据由来自目标晶片的反射光之间的干涉产生的干涉光的波长来测量光强度;信号处理器，其检测 当干扰光的强度根据波长变化时产生强度极值的时间点，以及将从信号处理器检测的极值产生时间点与对应于极值的参考时间点进行比较的控制器 产生时间点，并根据比较结果控制过程条件。

公开(公告)号：US20110295554A1

公开(公告)日：2011-12-01

申请号：US13115401

申请日：2011-05-25

申请人： Kye Hyun Baek ,  Sangwuk Park ,  Geum Jung Seong ,  Yongjin Kim

发明人： Kye Hyun Baek ,  Sangwuk Park ,  Geum Jung Seong ,  Yongjin Kim

IPC分类号： G06F19/00 ,  G06F15/00 ,  G06F17/10

CPC分类号： H01L21/3065 ,  G05B17/02 ,  H01J37/32853 ,  H01J37/3288 ,  H01J37/32981 ,  H01J37/3299

摘要： Disclosed is an apparatus for processing a semiconductor and a method for generating a seasoning process of a reaction chamber. The method may include generating plasma in the reaction chamber using a production process recipe, obtaining at least one reference measurement value related to a byproduct of the generated plasma, performing a plurality of seasoning tests on the chamber to obtain a plurality of test results, generating an empirical model by forming at least one relational expression correlating variables manipulated during the performing of the plurality of seasoning tests to the plurality of test results, and estimating a seasoning process by using the at least one relational expression to estimate at least one estimated calculation value.

摘要翻译： 公开了一种用于处理半导体的装置和用于产生反应室的调味过程的方法。 该方法可以包括使用生产工艺配方在反应室中产生等离子体，获得与产生的等离子体的副产物相关的至少一个参考测量值，在室上执行多个调味试验以获得多个测试结果，产生 通过形成至少一个关系表达式的经验模型，所述至少一个关系表达将在执行多个调味测试期间操纵的变量与多个测试结果相关联，并且通过使用至少一个关系表达式估计调节过程以估计至少一个估计的计算值 。

公开(公告)号：US20070099365A1

公开(公告)日：2007-05-03

申请号：US11586610

申请日：2006-10-26

申请人： Dong-Chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

发明人： Dong-Chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

IPC分类号： H01L21/8234

CPC分类号： H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4941 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656

摘要： An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers. The etching is preferably a process of etching the barrier layer in situ using an etchant having an etch selectivity between the material of the barrier layer and the materials constituting the other layers of the line.

摘要翻译： 半导体器件的集成电路具有不易发生严重RC延迟的线型图案。 该集成电路具有由至少一层多晶硅，具有低薄层电阻的金属层和介于多晶硅和具有低薄层电阻的金属之间的阻挡金属层形成的线，以及第一间隔物 分别布置在线的侧面上，其特征在于，线在阻挡层的侧面具有凹槽，并且第一间隔件填充凹部。 集成电路可以构成半导体器件的栅极线。 集成电路通过以下方式形成：将多层硅，具有低薄层电阻的金属和阻挡金属层叠在一起形成，将层图案化成一条线，蚀刻其形成凹部，然后形成第一间隔物。 蚀刻优选是使用在阻挡层的材料和构成线的其它层的材料之间具有蚀刻选择性的蚀刻剂原位蚀刻阻挡层的工艺。

公开(公告)号：US08872059B2

公开(公告)日：2014-10-28

申请号：US13220084

申请日：2011-08-29

申请人： Sang-Wuk Park ,  Geum-Jung Seong ,  Kye-Hyun Baek ,  Yong-Jin Kim ,  Chan-Mi Lee

发明人： Sang-Wuk Park ,  Geum-Jung Seong ,  Kye-Hyun Baek ,  Yong-Jin Kim ,  Chan-Mi Lee

IPC分类号： B23K26/03 ,  B23K26/04 ,  H01L21/00 ,  B23K26/06 ,  H01L21/66 ,  H01J37/32 ,  B23K26/36

CPC分类号： B23K26/0661 ,  B23K26/032 ,  B23K26/361 ,  H01J37/32972 ,  H01L22/12 ,  H01L22/26

摘要： Provided is an etching system and a method of controlling etching process condition. The etching system includes a light source that irradiates incident light into a target wafer, a light intensity measuring unit that measures light intensity according to the wavelength of interference light generated by interference between reflected light beams from the target wafer, a signal processor that detects a time point at which an extreme value in the intensity is generated when the intensity of interference light varies according to the wavelength, and a controller that compares the extreme value generating time point detected from the signal processor with a reference time point corresponding to the extreme value generating time point and controls a process condition according to the comparison result.

摘要翻译： 提供了蚀刻系统和控制蚀刻工艺条件的方法。 蚀刻系统包括将入射光照射到目标晶片中的光源，光强度测量单元，其根据由来自目标晶片的反射光之间的干涉产生的干涉光的波长来测量光强度;信号处理器，其检测 当干扰光的强度根据波长变化时产生强度极值的时间点，以及将从信号处理器检测的极值产生时间点与对应于极值的参考时间点进行比较的控制器 产生时间点，并根据比较结果控制过程条件。

公开(公告)号：US20080093663A1

公开(公告)日：2008-04-24

申请号：US11882654

申请日：2007-08-03

申请人： Jang-hee Lee ,  Gil-Heyun Choi ,  Byung-hee Kim ,  Tae-Ho Cha ,  Hee-Sook Park ,  Geum-Jung Seong

发明人： Jang-hee Lee ,  Gil-Heyun Choi ,  Byung-hee Kim ,  Tae-Ho Cha ,  Hee-Sook Park ,  Geum-Jung Seong

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： A method of forming a memory device includes forming a first insulating pattern and a polysilicon pattern in a peripheral region of a substrate, forming a cell gate insulating pattern including a second insulating pattern, a charge storage pattern, and a third insulating pattern in a cell region of the substrate, forming a barrier metal layer on the polysilicon pattern and on the third insulating pattern, forming a conductive layer on the barrier metal layer, patterning the conductive layer to simultaneously form a first conductive pattern on the polysilicon pattern and a second conductive pattern on the third insulating pattern, and patterning the barrier metal layer to simultaneously form a first barrier metal pattern on the polysilicon pattern and a second barrier metal pattern on the third insulating pattern.

摘要翻译： 形成存储器件的方法包括在衬底的周边区域中形成第一绝缘图案和多晶硅图案，在单元中形成包括第二绝缘图案，电荷存储图案和第三绝缘图案的单元栅极绝缘图案 在所述多晶硅图案和所述第三绝缘图案上形成阻挡金属层，在所述阻挡金属层上形成导电层，图案化所述导电层以同时在所述多晶硅图案上形成第一导电图案，并且将第二导电 图案化所述阻挡金属层，同时在所述多晶硅图案上形成第一阻挡金属图案，以及在所述第三绝缘图案上形成第二阻挡金属图案。

公开(公告)号：US07879737B2

公开(公告)日：2011-02-01

申请号：US12801115

申请日：2010-05-24

申请人： Woong-Hee Sohn ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Byung-Hak Lee ,  Tae-Ho Cha ,  Hee-Sook Park ,  Jae-Hwa Park ,  Geum-Jung Seong

发明人： Woong-Hee Sohn ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Byung-Hak Lee ,  Tae-Ho Cha ,  Hee-Sook Park ,  Jae-Hwa Park ,  Geum-Jung Seong

IPC分类号： H01L21/31

CPC分类号： H01L21/823481 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/2822 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78 ,  Y10S438/981

摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.

摘要翻译： 公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。 这些方法提供了常规GPOX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。 每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层 。 得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

公开(公告)号：US20110003455A1

公开(公告)日：2011-01-06

申请号：US12801115

申请日：2010-05-24

申请人： Woong-Hee SOHN ,  Gil-Heyun CHOI ,  Byung-Hee KIM ,  Byung-Hak LEE ,  Tae-Ho CHA ,  Hee-Sook PARK ,  Jae-Hwa PARK ,  Geum-Jung SEONG

发明人： Woong-Hee SOHN ,  Gil-Heyun CHOI ,  Byung-Hee KIM ,  Byung-Hak LEE ,  Tae-Ho CHA ,  Hee-Sook PARK ,  Jae-Hwa PARK ,  Geum-Jung SEONG

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/2822 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78 ,  Y10S438/981

摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPDX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPDX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.

摘要翻译： 公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。 这些方法提供了常规GPDX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPDX工艺相关的增加的栅电极电阻的程度。 每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层 。 得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

公开(公告)号：US07585787B2

公开(公告)日：2009-09-08

申请号：US11648595

申请日：2007-01-03

申请人： Tae-Ho Cha ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Hee-Sook Park ,  Jang-Hee Lee ,  Geum-Jung Seong

发明人： Tae-Ho Cha ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Hee-Sook Park ,  Jang-Hee Lee ,  Geum-Jung Seong

IPC分类号： H01L21/469

CPC分类号： H01L29/4941 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11568 ,  H01L29/513

摘要： A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.

摘要翻译： 半导体存储器件，例如电荷俘获型非易失性存储器件，可以包括形成在衬底的第一区域中的电荷俘获结构和形成在衬底的第二区域中的栅极结构。 电荷捕获结构可以包括隧道氧化物层图案，电荷俘获层图案和含铝三级金属氧化物的介电层图案。 栅极结构可以包括栅极氧化物层图案，多晶硅层图案和含铝三次金属硅化物的欧姆层图案。 第一电极和第二电极可以形成在电荷捕获结构上。 可以在栅极结构上设置下电极和上电极。 电介质层图案可以具有更高的介电常数，并且欧姆层图案可以具有改善的热稳定性，从而增强电荷俘获型非易失性存储器件的编程和擦除操作。

公开(公告)号：US20090011583A1

公开(公告)日：2009-01-08

申请号：US12165805

申请日：2008-07-01

申请人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Geum-Jung Seong

发明人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Geum-Jung Seong

IPC分类号： H01L21/28

CPC分类号： H01L21/28176 ,  H01L21/76826 ,  H01L27/10855 ,  H01L27/11521

摘要： A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.

摘要翻译： 在基板上形成栅极结构。 形成覆盖栅极结构的绝缘中间层。 在将绝缘中间层的表面暴露于氢气气氛的同时对基板进行热处理。 在热处理之后，在层间绝缘层上直接形成氮化硅层，在绝缘中间层上形成金属配线。 金属布线可以包括铜。 在将层间绝缘层的表面暴露于氢气气氛的同时对基板进行热处理之前，可以通过与基板接触的第一绝缘中间层形成插塞，并且金属布线可以电连接到插头。 插头可以包括钨。