公开(公告)号：US5696727A

公开(公告)日：1997-12-09

申请号：US742119

申请日：1996-10-31

申请人： Masaki Tsukude ,  Kazutami Arimoto ,  Shigeki Tomishima

发明人： Masaki Tsukude ,  Kazutami Arimoto ,  Shigeki Tomishima

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C11/4091 ,  G11C11/4096

摘要： A semiconductor memory device includes a memory cell, a word line, a bit line pair having a first bit line and a second bit line complementary to the first bit line, a p type well, first and second source lines, a source line precharge circuit for precharging the first and second source lines, a sense amplifier connected between the first and second bit lines, driven by the first and second source lines and including first and second n channel MOS transistors formed in the p type well and third and fourth p channel MOS transistors, a first sense amplifier enable transistor connected between a power supply potential node and the first source line, a second sense amplifier enable transistor connected between a ground potential node and the second source line, and a switching circuit connected between the first source line and the p type well, and turning on in response to a control signal when the sense amplifier is active.

摘要翻译： 半导体存储器件包括存储单元，字线，具有与第一位线互补的第一位线和第二位线的位线对，ap型阱，第一和第二源极线，源极线预充电电路， 对第一和​​第二源极线进行预充电，连接在由第一和第二源极线驱动的第一和第二位线之间的读出放大器，并且包括形成在p型阱中的第一和第二n沟道MOS晶体管以及第三和第四p沟道MOS 晶体管，连接在电源电位节点和第一源极线之间的第一读出放大器使能晶体管，连接在地电位节点和第二源极线之间的第二读出放大器使能晶体管，以及连接在第一源线和 p型良好，并且当感测放大器活动时响应于控制信号而导通。

公开(公告)号：US5694364A

公开(公告)日：1997-12-02

申请号：US779186

申请日：1997-01-06

申请人： Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

发明人： Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C29/00 ,  G11C29/06 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

CPC分类号： G11C5/147

摘要： In the normal mode, a first voltage-down converter down-converts an external power supply voltage to provide a large, first internal power supply voltage to the peripheral circuitry via a first internal power supply voltage supplying line, and a second voltage-down converter down-converts the external power supply voltage to provide a smaller, second internal power supply voltage to a memory cell array via a second internal power supply voltage supplying line. This allows fast operation and reduction in power consumption. In conducting a burn-in test, an external power supply voltage supplying line is connected to the first and second internal power supply voltage supplying lines. Thus, the first and second internal power supply voltage supplying lines directly receive the external power supply voltage. This allows an effective burn-in test. In a burn-in test, the first and second voltage-down converters are inactivated.

摘要翻译： 在正常模式中，第一降压转换器对外部电源电压进行下变频，以经由第一内部电源电压供应线向外围电路提供大的第一内部电源电压，以及第二降压转换器 降低外部电源电压，以经由第二内部电源电压供给线向存储单元阵列提供较小的第二内部电源电压。 这允许快速操作和降低功耗。 在进行老化试验时，外部电源电压供给线与第一和第二内部电源电压供给线连接。 因此，第一和第二内部电源电压供给线直接接收外部电源电压。 这允许有效的老化测试。 在老化测试中，第一和第二降压转换器失效。

公开(公告)号：US5659517A

公开(公告)日：1997-08-19

申请号：US486751

申请日：1995-06-06

申请人： Kazutami Arimoto ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C11/408 ,  G11C5/14 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/413 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H03K19/00 ,  G11C7/00

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C5/147

摘要： In a semiconductor integrated circuit device, a voltage setting circuit for setting a voltage level on the sub power source voltage line according to a reference voltage from a reference voltage generating circuit, is provided between a main power source voltage line and a sub power source voltage line. While a current consumption at the standby cycle is reduced, increase of the access delay is prevented. The voltage setting circuit includes a differential amplifier for differentially amplifying a voltage on the sub power source line and the reference voltages and a transistor responsive to an output of the differential amplifier for causing a current flow between the main and sub power source lines, or alternatively a diode-connected insulated gate type transistor receiving the reference voltage at a back gate thereof.

摘要翻译： 在半导体集成电路装置中，在主电源电压线和副电源电压之间设置用于根据来自基准电压发生电路的基准电压设定副电源电压线上的电压电平的电压设定电路 线。 虽然在备用周期的电流消耗减少，但是阻止了访问延迟的增加。 电压设定电路包括用于差分放大副电源线上的电压和参考电压的差分放大器，以及响应于差分放大器的输出以在主电源线和副电源线之间引起电流的晶体管，或者 二极管连接的绝缘栅型晶体管，在其后栅极接收参考电压。

公开(公告)号：US08169807B2

公开(公告)日：2012-05-01

申请号：US12261598

申请日：2008-10-30

申请人： Katsumi Dosaka ,  Kazutami Arimoto ,  Yoshio Matsuda

发明人： Katsumi Dosaka ,  Kazutami Arimoto ,  Yoshio Matsuda

IPC分类号： G11C15/00

CPC分类号： G06F17/30982 ,  G11C15/04 ,  Y02D10/45

摘要： In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other.

摘要翻译： 在内容可寻址存储器件中，在分别连接到第一和第二匹配线的两个TCAM单元中的搜索操作之前，存储器控制器将第一匹配线连接到电源，并将第二匹配线连接到地，然后将 第一和第二匹配线彼此之间，使得第一和第二匹配线的电位彼此相同。

公开(公告)号：US5375088A

公开(公告)日：1994-12-20

申请号：US149540

申请日：1993-11-09

申请人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

发明人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC分类号： G06F11/267 ,  G11C7/10 ,  G11C29/26 ,  G11C29/38 ,  G11C7/00

CPC分类号： G11C7/10 ,  G11C29/26 ,  G11C29/38 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G06F11/267

摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected to one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

摘要翻译： 可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。 数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。 在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。 在正常模式和测试模式下，输入数据被施加到连接到块之一的数据总线上，用于在写入期间同时在块中写入。 在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。 在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。

公开(公告)号：US5132930A

公开(公告)日：1992-07-21

申请号：US577062

申请日：1990-09-04

申请人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

发明人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC分类号： G11C11/4091 ,  G11C11/4097

CPC分类号： G11C11/4097 ,  G11C11/4091

摘要： In a metal-oxide semiconductor (MOS) dynamic formed on a semiconductor substrate, data nodes of a first flip-flop are connected to a first pair of folded bit lines. Its power supply node is connected through a switch to a first power supply (Vss). Data nodes of a second flip-flop are connected to a second pair of folded bit lines. Its power supply node is connected through a switch to the first power supply (Vss). A power supply node of a third flip-flop is connected through a switch to a second power supply (Vcc). Data nodes of the third flip-flop are coupled through a first pair of transfer gates to the first pair of the folded bit lines, and through a second pair of transfer gates to the second pair of the folded bit lines. Coupling the first to the third flip-flops forms a first sense amplifier and coupling the second to the third flip-flops forms a second sense amplifier.

摘要翻译： 在半导体衬底上形成的金属氧化物半导体（MOS）动态中，第一触发器的数据节点连接到第一对折叠位线。 其电源节点通过开关连接到第一电源（Vss）。 第二触发器的数据节点连接到第二对折叠位线。 其电源节点通过开关连接到第一电源（Vss）。 第三触发器的电源节点通过开关连接到第二电源（Vcc）。 第三触发器的数据节点通过第一对传输门耦合到第一对折叠位线，并通过第二对传输门耦合到第二对折叠位线。 耦合第一至第三触发器形成第一读出放大器并且将第二触发器耦合到第三触发器形成第二读出放大器。

公开(公告)号：US4788457A

公开(公告)日：1988-11-29

申请号：US94641

申请日：1987-09-09

申请人： Koichiro Mashiko ,  Kazutami Arimoto ,  Kiyohiro Furutani ,  Noriaki Matsumoto ,  Yoshio Matsuda

发明人： Koichiro Mashiko ,  Kazutami Arimoto ,  Kiyohiro Furutani ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC分类号： G11C11/408 ,  G11C8/10 ,  H03K17/693 ,  H03M7/00 ,  H03K19/096

CPC分类号： H03K17/693 ,  G11C8/10

摘要： A CMOS row decoder circuit in which a row decoder for selecting a single word line from a memory cell array and a column decoder for selecting a single bit line can use in common an internal address signal transmission line. The row decoder circuit comprises a series of MOSFETs of a first conductivity type which is turned on or off in response to address signals selected from external address signals, a second MOSFET of a second conductivity type provided between a power supply potential and the series of MOSFETs and having a gate receiving a first timing signal for providing decoding timing of the address signals, a third MOSFET of the first conductivity type provided between the series of MOSFETs and the second MOSFET and having a gate receiving a first operation timing signal, a fourth MOSFET which is turned on or off in response to a second operation timing signal for transmitting the potential of a node of the second MOSFET and the third MOSFET, and a fifth MOSFET having a gate receiving an output of the fourth MOSFET for transmitting a word line driving signal to a corresponding word line.

摘要翻译： 其中用于从存储单元阵列中选择单个字线的行解码器和用于选择单个位线的列解码器的CMOS行解码器电路可以共同地使用内部地址信号传输线。 行解码器电路包括响应于从外部地址信号中选择的地址信号而导通或截止的第一导电类型的一系列MOSFET，提供在电源电位和一系列MOSFET之间的第二导电类型的第二MOSFET 并且具有接收用于提供所述地址信号的解码定时的第一定时信号的栅极，设置在所述一系列MOSFET和所述第二MOSFET之间并具有接收第一操作定时信号的栅极的第一导电类型的第三MOSFET，第四MOSFET 其响应于用于传输第二MOSFET和第三MOSFET的节点的电位的第二操作定时信号而被接通或关断;以及第五MOSFET，其具有接收用于传输字线驱动的第四MOSFET的输出的栅极 信号到相应的字线。

公开(公告)号：US4873669A

公开(公告)日：1989-10-10

申请号：US77306

申请日：1987-07-24

申请人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

发明人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC分类号： G11C11/401 ,  G06F11/267 ,  G11C7/10 ,  G11C11/409 ,  G11C29/00 ,  G11C29/26 ,  G11C29/34 ,  G11C29/38

CPC分类号： G11C7/1057 ,  G11C29/26 ,  G11C29/38 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084 ,  G06F11/267

摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switches are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected to one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

摘要翻译： 可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。 数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。 读取和写入时，开关在正常模式下和写入期间在测试模式下导通，并且在测试模式下读取期间不导通。 在正常模式和测试模式下，输入数据被施加到连接到块之一的数据总线上，用于在写入期间同时在块中写入。 在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。 在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。

公开(公告)号：US4833518A

公开(公告)日：1989-05-23

申请号：US094646

申请日：1987-09-09

申请人： Yoshio Matsuda ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Kiyohiro Furutani

发明人： Yoshio Matsuda ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Kiyohiro Furutani

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L29/945 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/10829 ,  H01L2924/0002 ,  Y10S257/922 ,  Y10S257/929

摘要： A memory cell array is divided into two groups, one bit line of a pair of bit lines is connected to corresponding memory cells in the first group of the memory cell array, and the other bit line thereof is connected to corresponding memory cells in the second group of the memory cell array.

摘要翻译： 存储单元阵列被分成两组，一对位线的一个位线连接到存储单元阵列的第一组中的相应存储单元，而另一位与第二组中的相应存储单元连接 组的存储单元阵列。

公开(公告)号：US4817056A

公开(公告)日：1989-03-28

申请号：US077622

申请日：1987-07-24

申请人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

发明人： Kiyohiro Furutani ,  Koichiro Mashiko ,  Kazutami Arimoto ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/84

摘要： In a semiconductor memory device of a redundancy configuration having lines (rows or columns) of main memory cells and a line of spare memory cells made to substitute a defective line responsive to the address of the defective line, a comparator compares an address input to the memory device, with the address of the defective line which has been programmed in it, and a spare line selector selects the spare line when the input address is found to coincide with the programmed address. The comparator comprises a dynamic NOR gate having discharge paths each formed of a gate element receiving a bit or its inversion of the input address to be opened or closed depending on the value of the particular bit of the input address currently applied, and a PROM element in series with the gate element. The dynamic NOR gate has a first node forming an output thereof and a second node, each of the series connections of the PROM element and the gate element is connected across the first and the second nodes. The potential on the second node is caused to be identical with the potential on the first node during the precharge period.

摘要翻译： 在具有主存储单元的行（行或列）和响应于缺陷行的地址而替代缺陷行的备用存储单元的行的冗余配置的半导体存储器件中，比较器将输入到 存储器件，其中已经编程的缺陷线的地址，并且当发现输入地址与编程地址一致时，备用线选择器选择备用线。 该比较器包括一个动态或非门，每个放电路径均由栅极元件形成，栅极元件根据当前施加的输入地址的特定位的值接收要打开或关闭的输入地址的位或其反相，以及PROM元件 与门元件串联。 动态NOR门具有形成其输出的第一节点和第二节点，PROM元件和门元件的每个串联连接跨越第一节点和第二节点连接。 在预充电期间，使第二节点上的电位与第一节点上的电位相同。