公开(公告)号：US5949256A

公开(公告)日：1999-09-07

申请号：US961844

申请日：1997-10-31

申请人： Kevin Zhang ,  Jenny R. Carman

发明人： Kevin Zhang ,  Jenny R. Carman

IPC分类号： G11C17/18 ,  G11C7/06 ,  G11C11/409 ,  G11C11/419 ,  G11C16/06

CPC分类号： G11C7/065

摘要： An asymmetric sense amplifier is disclosed for use with single-ended memory arrays. The sense amplifier has a bit input, a reference input, an enable input, and bistable output circuitry. The reference input may simply be tied to V.sub.DD. The bistable output circuitry includes first and second output nodes disposed between first and second pull-up/pull-down paths, respectively. The first pull-up and pull-down paths may include first pull-up and pull-down FET channels, respectively. The second pull-up and pull-down paths may include second pull-up and pull-down FET channels, respectively. The bistable output circuitry is operable to be stable in first and second states. In both states, the output nodes are at opposite potentials. The sense amplifier is asymmetrical in the following sense: Either the second pull-down FET channel is wider than the first pull-down FET channel, or the first pull-up FET channel is wider than the second pull-up FET channel, or both. The result of the asymmetry is that the bistable output circuitry has a bias toward stabilizing in its first state. When the voltage on the bit input is equal to the voltage on the reference input and the enable input is asserted, the bistable output circuitry stabilizes in its first state; but when the voltage on the bit input is less than the voltage on the reference input by more than a threshold amount and the enable input is asserted, the bias is overcome and the bistable output circuitry stabilizes in its second state.

摘要翻译： 公开了一种用于单端存储器阵列的非对称读出放大器。 读出放大器具有位输入，参考输入，使能输入和双稳态输出电路。 参考输入可以简单地连接到VDD。 双稳态输出电路包括分别设置在第一和第二上拉/下拉路径之间的第一和第二输出节点。 第一上拉和下拉路径可以分别包括第一上拉和下拉FET通道。 第二上拉和下拉路径可以分别包括第二上拉和下拉FET通道。 双稳态输出电路可操作以在第一和第二状态下稳定。 在这两种状态下，输出节点处于相反的电位。 感测放大器在以下意义上是不对称的：第二下拉FET通道比第一下拉FET通道宽，或第一上拉FET通道比第二上拉FET通道宽，或两者均为 。 不对称的结果是双稳态输出电路具有在其第一状态下稳定的偏向。 当位输入上的电压等于参考输入上的电压并且使能输入被置位时，双稳态输出电路稳定在其第一状态; 但是当位输入上的电压小于参考输入上的电压超过阈值并且使能输入被断言时，该偏压被克服，并且双稳态输出电路稳定在其第二状态。

公开(公告)号：US08406073B1

公开(公告)日：2013-03-26

申请号：US12928948

申请日：2010-12-22

申请人： Dinesh Somasekhar ,  Gunjan Pandya ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Balaji Srinivasan ,  Swaroop Ghosh ,  Meterelliyoz Mesut

发明人： Dinesh Somasekhar ,  Gunjan Pandya ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Balaji Srinivasan ,  Swaroop Ghosh ,  Meterelliyoz Mesut

IPC分类号： G11C8/00

CPC分类号： G11C11/4097 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4094

摘要： A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.

摘要翻译： 采用本地位线对和全局位线的分级DRAM感测装置和方法。 字线选择感测放大器群集中的单元，每个放大器与一对位线相关联。 选择本地位线之一用于耦合到全局位线和全局读出放大器。 集群位于形成一个存储体的多个子阵列中，其中全局位线从每个存储体延伸到全局读出放大器。

公开(公告)号：US20110149666A1

公开(公告)日：2011-06-23

申请号：US12645623

申请日：2009-12-23

申请人： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang

发明人： Tsung-Yung Chang ,  Fatih Hamzaoglu ,  Gunjan H. Pandya ,  Siufu Chiu ,  Kevin Zhang

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C7/12 ,  G11C5/141 ,  G11C11/413

摘要： Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

摘要翻译： 公开了允许诸如SRAM的集成电路存储器中的功率节省的技术。 这些技术可以体现在允许位线漂移以消除或以其他方式减少与预充电位线相关联的功率泄漏的电路中。 例如，这些技术可以体现在具有用于通过唤醒信号对预充电控制信号进行限定的单个逻辑门的位线浮动电路中，从而如果唤醒信号不处于活动状态，则不会发生预充电位线。 这些技术还允许消除或减少I / O电路或存储器阵列的不必要的功率消耗，例如当存储器阵列未被访问时或者当阵列或其一部分被永久禁用以用于产量恢复时。

公开(公告)号：US20080292317A1

公开(公告)日：2008-11-27

申请号：US11943817

申请日：2007-11-21

申请人： Zhenli Wen ,  Kevin Zhang ,  Dongsheng Han ,  Fahua Lan

发明人： Zhenli Wen ,  Kevin Zhang ,  Dongsheng Han ,  Fahua Lan

IPC分类号： H04J14/02

CPC分类号： G02B6/29367 ,  G02B6/2938 ,  G02B6/4246

摘要： An apparatus for use in an optical transceiver module that incorporates an integrated multiplexer/demultiplexer for high speed data transfer applications. One example embodiment includes a transmissive block arranged to interface with a transmit optical port, a receive optical port, and a plurality of optical subassemblies. The transmit optical port may transmit a first multiplexed optical signal and the receive optical port may receive a second multiplexed optical signal. Filters may be positioned between the transmissive block and one or more of the optical subassemblies to transmit signals at predetermined wavelengths while reflecting other signals incident thereon.

摘要翻译： 一种用于光收发器模块的装置，其包括用于高速数据传输应用的集成多路复用器/解复用器。 一个示例实施例包括布置成与发射光端口，接收光端口和多个光学子组件接口的透射块。 发射光端口可以发送第一复用光信号，并且接收光端口可以接收第二复用光信号。 滤波器可以位于透射块和一个或多个光学子组件之间，以以预定波长传输信号，同时反射入射在其上的其它信号。

公开(公告)号：US20070153610A1

公开(公告)日：2007-07-05

申请号：US11323361

申请日：2005-12-29

申请人： Fatih Hamzaoglu ,  Kevin Zhang ,  Yih Wang

发明人： Fatih Hamzaoglu ,  Kevin Zhang ,  Yih Wang

IPC分类号： G11C5/14

CPC分类号： G11C5/146 ,  H03K19/0016

摘要： For one disclosed embodiment, circuitry may bias one or more wells of a substrate from a first state to a second state. Bias by the circuitry of one or more wells of the substrate to the second state may be boosted. Other embodiments are also disclosed.

摘要翻译： 对于一个所公开的实施例，电路可以将衬底的一个或多个阱从第一状态偏置到第二状态。 通过衬底的一个或多个孔的电路到第二状态的偏置可以被提升。 还公开了其他实施例。

公开(公告)号：US07228025B1

公开(公告)日：2007-06-05

申请号：US10698561

申请日：2003-10-31

申请人： Johnny Zhong ,  Yin Zhang ,  Steve Wang ,  Ping Xie ,  Kevin Zhang

发明人： Johnny Zhong ,  Yin Zhang ,  Steve Wang ,  Ping Xie ,  Kevin Zhang

IPC分类号： G02B6/26 ,  G02B6/42 ,  G02B6/32

CPC分类号： G02B6/2937 ,  G02B6/29386 ,  H04J14/02

摘要： A thin film interleaver device is disclosed. The thin film interleaver includes thin film optics. The thin film(s) are formed such that they reflect one group of wavelengths while allowing a second group of wavelengths to pass through the thin film(s). The thin film(s) exhibit a flat top frequency response across the channel bandwidths of the multiplexed signal for which the thin film filter is designed such that the thin film interleaver is less sensitive to wavelength drift and temperature variations.

摘要翻译： 公开了一种薄膜交织器件。 薄膜交织器包括薄膜光学器件。 薄膜形成为使得它们反射一组波长，同时允许第二组波长穿过薄膜。 该薄膜在多路复用信号的通道带宽上表现出平坦的顶频响应，薄膜滤波器被设计成使得薄膜交织器对波长漂移和温度变化较不敏感。

公开(公告)号：US20070058419A1

公开(公告)日：2007-03-15

申请号：US11225912

申请日：2005-09-13

申请人： Muhammad Khellah ,  Dinesh Somasekhar ,  Nam Kim ,  Yibin Ye ,  Vivek De ,  Kevin Zhang ,  Bo Zheng

发明人： Muhammad Khellah ,  Dinesh Somasekhar ,  Nam Kim ,  Yibin Ye ,  Vivek De ,  Kevin Zhang ,  Bo Zheng

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  Y10S257/903

摘要： For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.

公开(公告)号：US20050157537A1

公开(公告)日：2005-07-21

申请号：US11069775

申请日：2005-03-01

申请人： Liqiong Wei ,  Kevin Zhang

发明人： Liqiong Wei ,  Kevin Zhang

IPC分类号： G11C11/419 ,  G11C11/00

CPC分类号： G11C11/419

摘要： A method and apparatus for a four transistor SRAM comprising an array or block of cells. Each cell comprises a pair of pass transistors and a pair of pull-down transistors. In one embodiment of the invention, when the SRAM block is in a standby mode, the difference between the voltage at the gate and the voltage at the source of each pass transistor is greater than 0, and less than the threshold voltage of the pass transistor. In one embodiment of the invention a ground connection of the memory cell is switched such that when the SRAM block is in the standby mode, the ground connection is a virtual ground connection and when the SRAM block is in an active mode the ground connection is a global ground connection.

摘要翻译： 一种用于四晶体管SRAM的方法和装置，其包括阵列或单元块。 每个单元包括一对传输晶体管和一对下拉晶体管。 在本发明的一个实施例中，当SRAM块处于待机模式时，栅极电压与每个通过晶体管源极处的电压之差大于0，小于通过晶体管的阈值电压 。 在本发明的一个实施例中，切换存储器单元的接地连接，使得当SRAM块处于待机模式时，接地连接是虚拟接地连接，并且当SRAM块处于活动模式时，接地连接为 全球地面连接。

公开(公告)号：US06662333B1

公开(公告)日：2003-12-09

申请号：US09498496

申请日：2000-02-04

申请人： Kevin Zhang ,  Jenny R. C. Johnson

发明人： Kevin Zhang ,  Jenny R. C. Johnson

IPC分类号： G06F1110

CPC分类号： G06F11/1044

摘要： A shared error correcting circuit reduces memory overhead by sharing a fixed number of ECC bits among two or more memory units in a semiconductor memory. A single ECC block is used to generate check bits and syndrome bits. The ECC block tests each of the memory units by using the total number of ECC bits available in the ECC cells. Thus, the memory overhead is reduced from that in standard ECC designs.

摘要翻译： 共享纠错电路通过在半导体存储器中的两个或多个存储器单元之间共享固定数量的ECC位来减少存储器开销。 单个ECC块用于生成校验位和校验位。 ECC块通过使用ECC单元中可用的ECC位的总数来测试每个存储器单元。 因此，存储器开销从标准ECC设计中减少。